公开(公告)号：US20070132002A1

公开(公告)日：2007-06-14

申请号：US11502129

申请日：2006-08-09

申请人： YiPeng Chan ,  ShengHe Huang ,  Jing Lu

发明人： YiPeng Chan ,  ShengHe Huang ,  Jing Lu

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first OTP-EPROM gate overlying the gate dielectric layer in a first cell region, and an EEPROM floating gate and a select gate overlying the gate dielectric layer in a second cell region. An insulating layer is overlying the first OTP-EPROM gate, the EEPROM floating gate and the select gate. An OTP-EPROM control gate is overlying the insulating layer and coupled to the first OTP-EPROM gate. An EEPROM control gate is overlying the insulating layer and coupled to the EEPROM floating gate.

摘要翻译： 嵌入式EEPROM集成电路结构中OTP-EPROM的结构和制造方法。 该结构具有包括表面区域的基板。 该结构具有覆盖表面区域的栅极电介质。 该结构还包括覆盖第一单元区域中的栅极介电层的第一OTP-EPROM门，以及覆盖第二单元区域中的栅极介电层的EEPROM浮置栅极和选择栅极。 绝缘层覆盖着第一个OTP-EPROM门，EEPROM浮栅和选择门。 OTP-EPROM控制栅极覆盖绝缘层并耦合到第一个OTP-EPROM门。 EEPROM控制栅极覆盖绝缘层并耦合到EEPROM浮动栅极。

公开(公告)号：US20110133264A1

公开(公告)日：2011-06-09

申请号：US12959229

申请日：2010-12-02

申请人： YIPENG JAN ,  Zhen Yang ,  Shenghe Huang

发明人： YIPENG JAN ,  Zhen Yang ,  Shenghe Huang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/26586 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap.

摘要翻译： 一种用于制造电可擦除可编程只读存储器（EEPROM）器件的方法包括提供衬底并在衬底上形成栅极氧化物。 此外，该方法包括提供覆盖栅极氧化物层的掩模，掩模限定隧道开口。 该方法另外包括在掩模上执行选择性蚀刻以形成隧道氧化物层。 该方法包括在隧道氧化物层上形成浮置栅极，在栅极氧化物层上形成选择栅极。 该方法包括使用浮置栅极作为掩模对衬底的区域进行角度掺杂以获得第一掺杂区域。 所述方法还包括在所述浮动栅极上形成介电层和在所述电介质层上形成控制栅极。 该方法另外包括使用选择栅极作为掩模的角度掺杂衬底的第二区域以获得第二掺杂区域，其中第一和第二掺杂区域部分重叠。

公开(公告)号：US08470669B2

公开(公告)日：2013-06-25

申请号：US12959229

申请日：2010-12-02

申请人： Yipeng Jan ,  Zhen Yang ,  Shenghe Huang

发明人： Yipeng Jan ,  Zhen Yang ,  Shenghe Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/28273 ,  H01L21/26586 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap.

摘要翻译： 一种用于制造电可擦除可编程只读存储器（EEPROM）器件的方法包括提供衬底并在衬底上形成栅极氧化物。 此外，该方法包括提供覆盖栅极氧化物层的掩模，掩模限定隧道开口。 该方法另外包括在掩模上执行选择性蚀刻以形成隧道氧化物层。 该方法包括在隧道氧化物层上形成浮置栅极，在栅极氧化物层上形成选择栅极。 该方法包括使用浮置栅极作为掩模对衬底的区域进行角度掺杂以获得第一掺杂区域。 所述方法还包括在所述浮动栅极上形成介电层和在所述电介质层上形成控制栅极。 该方法另外包括使用选择栅极作为掩模的角度掺杂衬底的第二区域以获得第二掺杂区域，其中第一和第二掺杂区域部分重叠。

公开(公告)号：US07736967B2

公开(公告)日：2010-06-15

申请号：US11502129

申请日：2006-08-09

申请人： YiPeng Chan ,  ShengHe Huang ,  Jing Lu

发明人： YiPeng Chan ,  ShengHe Huang ,  Jing Lu

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A structure and a manufacturing method for an OTP-EPROM in an embedded EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. The structure has a gate dielectric is overlying the surface region. The structure also a first OTP-EPROM gate overlying the gate dielectric layer in a first cell region, and an EEPROM floating gate and a select gate overlying the gate dielectric layer in a second cell region. An insulating layer is overlying the first OTP-EPROM gate, the EEPROM floating gate and the select gate. An OTP-EPROM control gate is overlying the insulating layer and coupled to the first OTP-EPROM gate. An EEPROM control gate is overlying the insulating layer and coupled to the EEPROM floating gate.

摘要翻译： 嵌入式EEPROM集成电路结构中OTP-EPROM的结构和制造方法。 该结构具有包括表面区域的基板。 该结构具有覆盖表面区域的栅极电介质。 该结构还包括覆盖第一单元区域中的栅极介电层的第一OTP-EPROM门，以及覆盖第二单元区域中的栅极介电层的EEPROM浮置栅极和选择栅极。 绝缘层覆盖着第一个OTP-EPROM门，EEPROM浮栅和选择门。 OTP-EPROM控制栅极覆盖绝缘层并耦合到第一个OTP-EPROM门。 EEPROM控制栅极覆盖绝缘层并耦合到EEPROM浮动栅极。