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    Locking active stylus and touch-sensor device
    1.
    发明授权
    Locking active stylus and touch-sensor device 有权

    公开(公告)号：US09690431B2

    公开(公告)日：2017-06-27

    申请号：US13328055

    申请日：2011-12-16

    申请人： Shahrooz Shahparnia ,  Sherif Hanna

    发明人： Shahrooz Shahparnia ,  Sherif Hanna

    IPC分类号： A61B1/005 ,  G06F3/044 ,  G06F3/0354 ,  G06F3/038

    CPC分类号： G06F3/044 ,  G06F3/03545 ,  G06F3/0383

    摘要： In one embodiment, a system comprises a touch sensor and a stylus. The touch sensor comprises drive lines and sense lines arranged such that intersections of the drive lines and sense lines form capacitive nodes. The drive lines transmits a first signal having an identification portion. The stylus comprises a sense unit and a drive unit. The sense unit senses the first signal from the drive lines, compares the identification portion to criteria stored in the stylus, and authorizes the drive unit to transmit a second signal based on the first signal if the identification portion satisfies the criteria stored in the stylus. The drive unit transmits the second signal to the sense lines such that transmission of the second signal changes capacitance of the capacitive nodes.

    Method and circuitry to translate a differential logic signal to a CMOS logic signal
    5.
    发明授权
    Method and circuitry to translate a differential logic signal to a CMOS logic signal 有权
    将差分逻辑信号转换为CMOS逻辑信号的方法和电路

    公开(公告)号：US07777521B2

    公开(公告)日：2010-08-17

    申请号：US11986980

    申请日：2007-11-27

    申请人： Sherif Hanna ,  Greg J. Landry ,  Alan ReFalo ,  Jeyenth Vijayaraghavan

    发明人： Sherif Hanna ,  Greg J. Landry ,  Alan ReFalo ,  Jeyenth Vijayaraghavan

    IPC分类号： H03K19/094 ,  H03K19/0175

    CPC分类号： H03K19/018528 ,  H03K19/0948

    摘要： Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

    摘要翻译： 公开了差分逻辑到CMOS逻辑转换器的各种实施例，其包括电平移位和缓冲级，其被配置为接收差分输入并提供具有较低共模电压的结果信号。 此外，包括增益级以接收所得到的信号并提供增加的摆动信号。 还包括CMOS缓冲器，并配置为接收增加的摆幅信号并提供CMOS逻辑输出。 还公开了一种将差分逻辑信号转换为包括电平移位和缓冲差分输入信号的CMOS逻辑信号以提供具有较低共模电压的结果信号的方法。 该方法还包括使用增益级从所得到的较低共模信号提供增加的摆幅信号，并使用CMOS缓冲器从增加的摆动信号提供CMOS输出。

    High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
    6.
    发明申请
    High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion 有权
    具有低数据相关抖动和占空比失真的CMOS转换器架构的高速差分逻辑

    公开(公告)号：US20080143385A1

    公开(公告)日：2008-06-19

    申请号：US11986980

    申请日：2007-11-27

    申请人： Sherif Hanna ,  Greg J. Landry ,  Alan ReFalo ,  Jeyenth Vijayaraghavan

    发明人： Sherif Hanna ,  Greg J. Landry ,  Alan ReFalo ,  Jeyenth Vijayaraghavan

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018528 ,  H03K19/0948

    摘要： Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

    摘要翻译： 公开了差分逻辑到CMOS逻辑转换器的各种实施例，其包括电平移位和缓冲级，其被配置为接收差分输入并提供具有较低共模电压的结果信号。 此外，包括增益级以接收所得到的信号并提供增加的摆动信号。 还包括CMOS缓冲器，并配置为接收增加的摆幅信号并提供CMOS逻辑输出。 还公开了一种将差分逻辑信号转换为包括电平移位和缓冲差分输入信号的CMOS逻辑信号以提供具有较低共模电压的结果信号的方法。 该方法还包括使用增益级从所得到的较低共模信号提供增加的摆幅信号，并使用CMOS缓冲器从增加的摆动信号提供CMOS输出。

    High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion
    7.
    发明授权
    High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion 有权
    具有低数据相关抖动和占空比失真的CMOS转换器架构的高速差分逻辑

    公开(公告)号：US07301370B1

    公开(公告)日：2007-11-27

    申请号：US10852272

    申请日：2004-05-24

    申请人： Sherif Hanna ,  Greg J. Landry ,  Alan ReFalo ,  Jeyenth Vijayaraghavan

    发明人： Sherif Hanna ,  Greg J. Landry ,  Alan ReFalo ,  Jeyenth Vijayaraghavan

    IPC分类号： H03K19/094 ,  H03K19/0175

    CPC分类号： H03K19/018528 ,  H03K19/0948

    摘要： Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

    摘要翻译： 公开了差分逻辑到CMOS逻辑转换器的各种实施例，其包括电平移位和缓冲级，其被配置为接收差分输入并提供具有较低共模电压的结果信号。 此外，包括增益级以接收所得到的信号并提供增加的摆动信号。 还包括CMOS缓冲器，并配置为接收增加的摆幅信号并提供CMOS逻辑输出。 还公开了一种将差分逻辑信号转换为包括电平移位和缓冲差分输入信号的CMOS逻辑信号以提供具有较低共模电压的结果信号的方法。 该方法还包括使用增益级从所得到的较低共模信号提供增加的摆幅信号，并使用CMOS缓冲器从增加的摆动信号提供CMOS输出。

    Locking Active Stylus and Touch-Sensor Device
    9.
    发明申请
    Locking Active Stylus and Touch-Sensor Device 有权
    锁定主动触笔和触摸感应器

    公开(公告)号：US20130106762A1

    公开(公告)日：2013-05-02

    申请号：US13328055

    申请日：2011-12-16

    申请人： Shahrooz Shahparnia ,  Sherif Hanna

    发明人： Shahrooz Shahparnia ,  Sherif Hanna

    IPC分类号： G06F3/044

    CPC分类号： G06F3/044 ,  G06F3/03545 ,  G06F3/0383

    摘要： In one embodiment, a system comprises a touch sensor and a stylus. The touch sensor comprises drive lines and sense lines arranged such that intersections of the drive lines and sense lines form capacitive nodes. The drive lines transmits a first signal having an identification portion. The stylus comprises a sense unit and a drive unit. The sense unit senses the first signal from the drive lines, compares the identification portion to criteria stored in the stylus, and authorizes the drive unit to transmit a second signal based on the first signal if the identification portion satisfies the criteria stored in the stylus. The drive unit transmits the second signal to the sense lines such that transmission of the second signal changes capacitance of the capacitive nodes.

    摘要翻译： 在一个实施例中，系统包括触摸传感器和触笔。 触摸传感器包括驱动线和感测线，其布置成使得驱动线和感测线的交点形成电容性节点。 驱动线发送具有识别部分的第一信号。 触针包括感测单元和驱动单元。 感测单元感测来自驱动线的第一信号，将识别部分与存储在触控笔中的标准进行比较，并且如果识别部分满足存储在触笔中的标准，则授权驱动单元基于第一信号发送第二信号。 驱动单元将第二信号发送到感测线，使得第二信号的传输改变电容性节点的电容。