公开(公告)号：US07608908B1

公开(公告)日：2009-10-27

申请号：US12125613

申请日：2008-05-22

申请人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

IPC分类号： H01L29/00 ,  H01L29/167

CPC分类号： H01L21/76264

摘要： Higher voltage device isolation structures (40, 60, 70, 80, 90, 90′) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24″). One or more dielectric lined deep isolation trenches (27, 27′, 27″, 27′″) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22″) is found to occur preferentially where the buried layer (24, 24″) intersects the dielectric sidewalls (273, 274; 273′, 274′; 273″, 274″) of the trench (27, 27′, 27″, 27′″). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42″, 62, 72, 82) of the same conductivity type as the buried layer (24, 24″), underlying the buried layer (24, 24″) at the trench sidewalls (273, 274; 273′, 274′; 273″, 274″). The more lightly doped region's (42, 42″, 62, 72, 82) dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (24, 24″) and it extends substantially entirely beneath the buried layer (24, 24″) or to a distance (724, 824) extending about 0.5 to 2.0 micro-meters from the trench sidewall (273, 274; 273′, 274′; 273″, 274″). In a preferred embodiment, the trench (27, 27′) is split into two portions (271, 272; 271′, 272′) with the semiconductor therein (475, 675, 775, 875) ohmically coupled to the substrate (22).

摘要翻译： 为具有强掺杂掩埋层（24,24“）的半导体集成电路提供更高电压器件隔离结构（40,60,70,80,90,90'）。 一个或多个电介质衬里的深隔离沟槽（27,27'，27“，27”'）分隔相邻的器件区域（411,412; 611,612; 711,712; 811,812; 911,912）。 发现器件区域（411,412; 611,612; 711,712; 811,812; 911,912）和相对掺杂的衬底（22,22“）之间的电击穿（BVdss）优先发生在埋置 层（24,24“）与沟槽（27,27'，27”，27“'）的电介质侧壁（273,274; 273'，274'; 273”，274“）相交。 通过提供与掩埋层下面的掩埋层（24,24“）相同的导电类型的更轻掺杂区域（42,42”，62,72,82）来增加击穿电压（BVdss） （273,274; 273'，274'; 273“，”274“）上。 掺杂浓度越高的掺杂区越好，比掩埋层（24,24“）要小1〜4埃，比埋入层（24，24”）大致全部下降， 距离沟槽侧壁（273,274; 273'，274'; 273“，”274“）延伸约0.5至2.0微米的距离（724,824）。 在优选实施例中，沟槽（27,27'）被分成两部分（271,272; 271'，272'），其中半导体在其中欧姆耦合到衬底（22），其中（475,675,775,875） 。