公开(公告)号：US07608908B1

公开(公告)日：2009-10-27

申请号：US12125613

申请日：2008-05-22

申请人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Michael C. Butner ,  Bernhard H. Grote ,  Tahir A. Khan ,  Shifeng Shen ,  Ronghua Zhu

IPC分类号： H01L29/00 ,  H01L29/167

CPC分类号： H01L21/76264

摘要： Higher voltage device isolation structures (40, 60, 70, 80, 90, 90′) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24″). One or more dielectric lined deep isolation trenches (27, 27′, 27″, 27′″) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22″) is found to occur preferentially where the buried layer (24, 24″) intersects the dielectric sidewalls (273, 274; 273′, 274′; 273″, 274″) of the trench (27, 27′, 27″, 27′″). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42″, 62, 72, 82) of the same conductivity type as the buried layer (24, 24″), underlying the buried layer (24, 24″) at the trench sidewalls (273, 274; 273′, 274′; 273″, 274″). The more lightly doped region's (42, 42″, 62, 72, 82) dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (24, 24″) and it extends substantially entirely beneath the buried layer (24, 24″) or to a distance (724, 824) extending about 0.5 to 2.0 micro-meters from the trench sidewall (273, 274; 273′, 274′; 273″, 274″). In a preferred embodiment, the trench (27, 27′) is split into two portions (271, 272; 271′, 272′) with the semiconductor therein (475, 675, 775, 875) ohmically coupled to the substrate (22).

摘要翻译： 为具有强掺杂掩埋层（24,24“）的半导体集成电路提供更高电压器件隔离结构（40,60,70,80,90,90'）。 一个或多个电介质衬里的深隔离沟槽（27,27'，27“，27”'）分隔相邻的器件区域（411,412; 611,612; 711,712; 811,812; 911,912）。 发现器件区域（411,412; 611,612; 711,712; 811,812; 911,912）和相对掺杂的衬底（22,22“）之间的电击穿（BVdss）优先发生在埋置 层（24,24“）与沟槽（27,27'，27”，27“'）的电介质侧壁（273,274; 273'，274'; 273”，274“）相交。 通过提供与掩埋层下面的掩埋层（24,24“）相同的导电类型的更轻掺杂区域（42,42”，62,72,82）来增加击穿电压（BVdss） （273,274; 273'，274'; 273“，”274“）上。 掺杂浓度越高的掺杂区越好，比掩埋层（24,24“）要小1〜4埃，比埋入层（24，24”）大致全部下降， 距离沟槽侧壁（273,274; 273'，274'; 273“，”274“）延伸约0.5至2.0微米的距离（724,824）。 在优选实施例中，沟槽（27,27'）被分成两部分（271,272; 271'，272'），其中半导体在其中欧姆耦合到衬底（22），其中（475,675,775,875） 。

公开(公告)号：US06930027B2

公开(公告)日：2005-08-16

申请号：US10369874

申请日：2003-02-18

申请人： Vijay Parthasarathy ,  Vishnu Khemka ,  Ronghua Zhu ,  Amitava Bose ,  Todd Roggenbauer ,  Paul Hui ,  Michael C. Butner

发明人： Vijay Parthasarathy ,  Vishnu Khemka ,  Ronghua Zhu ,  Amitava Bose ,  Todd Roggenbauer ,  Paul Hui ,  Michael C. Butner

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/425

CPC分类号： H01L21/3081 ,  H01L21/76229

摘要： A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.

摘要翻译： 制造半导体部件的方法包括在半导体衬底（110）上形成第一电绝缘层（120）和第二电绝缘层（130）。 该方法还包括通过第一和第二电绝缘层蚀刻第一沟槽（140）和第二沟槽（150）并进入半导体衬底，以及通过第二沟槽的底表面蚀刻第三沟槽（610）并且进入 半导体衬底。 第三沟槽在第一部分内部具有第一部分（920）和第二部分（930）。 该方法还包括形成填充第一沟槽和第三沟槽的第一部分的第三电绝缘层（910），而不填充第三沟槽的第二部分，并且还包括在第二部分中形成插塞层（1010） 的第三沟。

公开(公告)号：US20070221967A1

公开(公告)日：2007-09-27

申请号：US11390796

申请日：2006-03-27

申请人： Vishnu Khemka ,  Amitava Bose ,  Todd Roggenbauer ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Todd Roggenbauer ,  Ronghua Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7816

摘要： A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).

摘要翻译： 半导体器件可以包括具有第一掺杂剂类型的半导体衬底。 半导体衬底内的第一半导体区域可以具有多个第一和第二部分（44,45）。 第一部分（44）可以具有第一厚度，并且第二部分（54）可以具有第二厚度。 第一半导体区域可以具有第二掺杂剂类型。 半导体衬底内的多个第二半导体区域（42）可以各自定位在第一半导体区域的第一部分（44）的相应一个的正下方并直接位于第一半导体区域的第一部分（44）的下方中的至少一个，并且横向地位于相应的一对第二半导体区域 第一半导体区域的部分（54）。 半导体衬底内的第三半导体区域（56）可以具有第一掺杂剂类型。 栅电极（64）可以在第一半导体区域的至少一部分和第三半导体区域（56）的至少一部分之上。

公开(公告)号：US20070200136A1

公开(公告)日：2007-08-30

申请号：US11364769

申请日：2006-02-28

申请人： Ronghua Zhu ,  Vishnu Khemka ,  Amitava Bose ,  Todd Roggenbauer

发明人： Ronghua Zhu ,  Vishnu Khemka ,  Amitava Bose ,  Todd Roggenbauer

IPC分类号： H01L29/00

CPC分类号： H01L29/866 ,  H01L29/0692

摘要： The present disclosure relates to isolated Zener diodes (100) that are substantially free of substrate current injection when forward biased. In particular, the Zener diodes (100) include an “isolation tub” structure that includes surrounding walls (150, 195) and a base (130) formed of semiconductor regions. In addition, the diodes (100) include silicide block (260) extending between anode (210) and cathode (220) regions. The reduction or elimination of substrate current injection overcomes a significant shortcoming of conventional Zener diodes that generally all suffer from substrate current injection when they are forward biased. Due to this substrate current injection, the current from each of a conventional diode's two terminals is not the same.

摘要翻译： 本公开涉及在正向偏置时基本上不含衬底电流注入的隔离齐纳二极管（100）。 特别地，齐纳二极管（100）包括包括由半导体区形成的周围壁（150,195）和基座（130）的“隔离桶”结构。 此外，二极管（100）包括在阳极（210）和阴极（220）区域之间延伸的硅化物块（260）。 衬底电流注入的减少或消除克服了常规齐纳二极管的显着缺点，当它们正向偏置时，其通常都遭受衬底电流注入。 由于这种衬底电流注入，来自常规二极管的两个端子中的每一个的电流是不相同的。

公开(公告)号：US20060267089A1

公开(公告)日：2006-11-30

申请号：US11142111

申请日：2005-05-31

申请人： Vishnu Khemka ,  Amitava Bose ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Ronghua Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7393 ,  H01L29/66325

摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200) that includes a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130) having the second conductivity type located above at least a portion of the first semiconductor region, an emitter (150) having the second conductivity type disposed in the second semiconductor region, and a collector (170) having the second conductivity type disposed in the first semiconductor region. A sinker region (140) is provided to electrically tie the buried semiconductor region (115) to the second semiconductor region (130). In a particular embodiment, the second semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias potential applied across the semiconductor component.

摘要翻译： 一种半导体元件和制造方法，包括绝缘栅双极晶体管（IGBT）（100,200），其包括具有第一导电类型的半导体衬底（110）和具有第二导电类型的掩埋半导体区域（115） 半导体衬底。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120），具有位于第一半导体区域的至少一部分上方的第二导电类型的第二半导体区域（130），发射极 150），并且具有设置在第一半导体区域中的具有第二导电类型的集电极（170）。 提供沉降片区域（140）以将掩埋的半导体区域（115）电连接到第二半导体区域（130）。 在特定实施例中，响应于施加在半导体部件上的反向偏置电位，第二半导体区域和掩埋半导体区域耗尽第一半导体区域。

公开(公告)号：US20050242371A1

公开(公告)日：2005-11-03

申请号：US10836730

申请日：2004-04-30

申请人： Vishnu Khemka ,  Amitava Bose ,  Vijay Parthasarathy ,  Ronghua Zhu

发明人： Vishnu Khemka ,  Amitava Bose ,  Vijay Parthasarathy ,  Ronghua Zhu

IPC分类号： H01L27/07 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/0847 ,  H01L27/0722 ,  H01L29/42368 ,  H01L29/7835

摘要： Particularly in high current applications, impact ionization induced electron-hole pairs are generated in the drain of an MOS transistor that can cause a parasitic bipolar transistor to become destructively conductive. The holes pass through the body region of the MOS transistor, which has intrinsic resistance, to the source, which is typically held at a relatively low voltage, such as ground. The hole current causes a voltage to develop in the body region, which acts as the base. This increased base voltage is what can cause the parasitic bipolar transistor to become conductive. The likelihood of this is greatly reduced by developing a voltage between the source, which acts as the emitter, and the body region by passing the channel current through an impedance between the source and the body region. This causes the emitter voltage to increase as the base voltage is increased and thereby prevent the parasitic bipolar transistor from becoming conductive.

摘要翻译： 特别是在高电流应用中，在MOS晶体管的漏极中产生电子 - 电子碰撞的碰撞对，这可使寄生双极晶体管变得具有破坏性的导电性。 这些孔通过具有固有电阻的MOS晶体管的体区通向保持在较低电压（例如地）的源极。 空穴电流导致在作为基底的身体区域中产生电压。 这种增加的基极电压可以导致寄生双极晶体管导通。 通过使通道电流通过源极和体区之间的阻抗，在作为发射极的源与体区之间形成电压，大大降低了这种可能性。 这导致发射极电压随着基极电压的增加而增加，从而防止寄生双极晶体管导通。

公开(公告)号：US06750524B2

公开(公告)日：2004-06-15

申请号：US10145524

申请日：2002-05-14

申请人： Vijay Parthasarthy ,  Vishnu Khemka ,  Ronghua Zhu ,  Amitava Bose

发明人： Vijay Parthasarthy ,  Vishnu Khemka ,  Ronghua Zhu ,  Amitava Bose

IPC分类号： H01L2358

CPC分类号： H01L29/402 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： A RESURF super-junction device (51) is provided which comprises a plurality of electrodes (53) disposed in a layer of a first material (61) having a first conductivity type. Each of the plurality of electrodes contains a second material (57) of a second conductivity type which is encased in a dielectric material (55).

摘要翻译： 提供了RESURF超接合器件（51），其包括设置在具有第一导电类型的第一材料（61）的层中的多个电极（53）。 多个电极中的每一个包含第二导电类型的第二材料（57），其被封装在电介质材料（55）中。

公开(公告)号：US20090174030A1

公开(公告)日：2009-07-09

申请号：US11969600

申请日：2008-01-04

申请人： Tahir A. Khan ,  Amitava Bose ,  Vishnu K. Khemka ,  Ronghua Zhu

发明人： Tahir A. Khan ,  Amitava Bose ,  Vishnu K. Khemka ,  Ronghua Zhu

IPC分类号： H01L21/283 ,  H01L29/94

CPC分类号： H01L29/94 ,  H01L21/86 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66181

摘要： Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.

摘要翻译： 对于MOS电容器（MOS CAP）描述了方法（200）和装置（30,50-53）。 装置（30,50-53）包括具有由电介质（35,57,95）覆盖的欧姆耦合的N和P半导体区域（32,34; 54,56; 92,94）的衬底（31）。 导电电极（36,58,96）覆盖在这些N和P区域（32,34; 54,56; 92,94）上方的电介质（35,57,95）上。 使用欧姆耦合的N和P区域（32,34; 54,56; 92,94）通过与普通MOS CAP相关联的施加电压基本上减小电容的变化（40,64,70,80）。 当这些N和P区域（32,34; 54,56; 92,94）具有不同的掺杂时，电容变化（40,64,70,80）仍然可以通过调节电介质的性质（57， （54,56; 92,94）的N区域和/或P区域（54,56; 92,94）或两者的相对区域之间。 因此，这样的MOS CAPS可以更容易地与其他半导体器件集成，对所建立的集成电路（IC）制造过程具有最小或没有干扰，并且不会显着地增加超过常规MOS CAP所需的占用面积。

公开(公告)号：US09397233B2

公开(公告)日：2016-07-19

申请号：US12791996

申请日：2010-06-02

申请人： Ronghua Zhu ,  Vishnu Khemka ,  Amitava Bose ,  Todd C. Roggenbauer

发明人： Ronghua Zhu ,  Vishnu Khemka ,  Amitava Bose ,  Todd C. Roggenbauer

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L27/13 ,  H01L49/02 ,  H01L29/66

CPC分类号： H01L29/94 ,  H01L27/13 ,  H01L28/91 ,  H01L29/66181

摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).

摘要翻译： 半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。 深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。 第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

公开(公告)号：US07309638B2

公开(公告)日：2007-12-18

申请号：US11182597

申请日：2005-07-14

申请人： Vishnu Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose ,  Todd C. Roggenbauer

发明人： Vishnu Khemka ,  Vijay Parthasarathy ,  Ronghua Zhu ,  Amitava Bose ,  Todd C. Roggenbauer

IPC分类号： H01L21/20 ,  H01L21/00

CPC分类号： H01L29/866 ,  H01L27/0255 ,  H01L27/0814 ,  Y10S438/983

摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.

摘要翻译： 半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320） ，340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域 半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。 在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。 在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。