公开(公告)号：US4747154A

公开(公告)日：1988-05-24

申请号：US655690

申请日：1984-09-28

申请人： Kazufumi Suzuki ,  Katsura Kawakami ,  Shigeo Shimazaki ,  Yuetsu Ochiai ,  Etsuko Hirokami ,  Hiroaki Kotera

发明人： Kazufumi Suzuki ,  Katsura Kawakami ,  Shigeo Shimazaki ,  Yuetsu Ochiai ,  Etsuko Hirokami ,  Hiroaki Kotera

IPC分类号： G06T3/40 ,  G06K9/42

CPC分类号： G06T3/4023

摘要： An apparatus for expanding or contracting image data includes an input for storing the image data to be processed, a first barrel shifter for shifting the output data of the input register, a control register for storing a mapping pattern which indicates a position of the image data bits to be extracted in the expansion mode or which indicates the number of times when the image data are to be copied, an expansion and contraction circuit for expanding or contracting the image data by referring to the mapping pattern, and a second barrel register for shifting the output image data of the expansion and contraction circuit before the data are loaded in an output data register.

摘要翻译： 用于扩展或缩小图像数据的装置包括用于存储要处理的图像数据的输入，用于移位输入寄存器的输出数据的第一桶形移位器，用于存储指示图像数据的位置的映射模式的控制寄存器 要在扩展模式中提取的位或指示要复制图像数据的次数，用于通过参考映射模式来扩展或缩小图像数据的扩展和缩小电路以及用于移位的第二桶寄存器 将数据加载到输出数据寄存器之前的扩展和收缩电路的输出图像数据。

公开(公告)号：US4602346A

公开(公告)日：1986-07-22

申请号：US612010

申请日：1984-05-18

申请人： Katsura Kawakami ,  Shigeo Shimazaki ,  Etsuko Hirokami

发明人： Katsura Kawakami ,  Shigeo Shimazaki ,  Etsuko Hirokami

IPC分类号： G06T3/00 ,  G06F15/20

CPC分类号： G06T3/0006

摘要： Image data is transposed between successively arranged first data points in a first image field and successively arranged second data points in a second image field by a method comprising: (1) successively specifying a first data point (i); (2) summing first control data indicative of a residue with second control data indicative of a constant value; (3.sub.1) if the result of the summation does not exceed a predetermined value, updating the first control data with the summation result and specifying a second data point (j) corresponding to the specified first data point, or (3.sub.2) if the result exceeds the predetermined value, subtracting it from the summation result to update the first control data with the residue, and specifying a second data point (j) which is shifted by one data point with respect to the specified first data point; (4) transferring the image data from the specified first data point to the specified second data point or from the specified second data point to the specified first data point depending on the relative size of the first and second image fields. The steps (1) to (4) are repeated until all the second data points are filled with the image data.

摘要翻译： 图像数据被转置在第一图像场中的连续排列的第一数据点之间，并且通过以下方法连续布置在第二图像场中的第二数据点：（1）连续指定第一数据点（i）; （2）用指示恒定值的第二控制数据对表示残差的第一控制数据求和; （31）如果求和的结果不超过预定值，则用求和结果更新第一控制数据并指定与指定的第一数据点相对应的第二数据点（j），或（32）如果结果超过 所述预定值从所述求和结果中减去以更新所述第一控制数据，并且指定相对于所述指定的第一数据点偏移了一个数据点的第二数据点（j）; （4）根据第一和第二图像场的相对大小，将图像数据从指定的第一数据点传送到指定的第二数据点或从指定的第二数据点传送到指定的第一数据点。 重复步骤（1）至（4），直到所有第二数据点被填充有图像数据。

公开(公告)号：US4392198A

公开(公告)日：1983-07-05

申请号：US169472

申请日：1980-07-16

申请人： Shigeo Shimazaki

发明人： Shigeo Shimazaki

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/32

CPC分类号： G06F9/261

摘要： A central processing unit of a computer system comprises a programmable logic array which is constructed of an AND matrix and an OR matrix. The AND matrix is responsive to a machine language instruction and to a number of a region for selecting one row from a plurality of rows arranged in the AND matrix. The OR matrix, which also has a plurality of rows, is responsive to the selected row for selecting one row therefrom. In each of the rows of the OR matrix a microaddress and a number of a region to be used for producing a subsequent microaddress are prewritten so that information on a microaddress and information on a region number are respectively obtained. At least one microinstruction included in a microprogram will be read out from a read-only memory in accordance with the obtained microaddress to execute the same, while a microaddress of a subsequent microprogram is produced in the programmable logic array. Namely the execution of a microprogram routine and the production of the first address of a following microprogram routine are concurrently performed so that efficient execution of microprograms can be achieved, while each microinstruction is not required to include region number information.

摘要翻译： 计算机系统的中央处理单元包括由AND矩阵和OR矩阵构成的可编程逻辑阵列。 AND矩阵响应于机器语言指令和多个用于从AND矩阵中排列的多个行中选择一行的区域。 还具有多行的OR矩阵响应于所选择的行从其中选择一行。 在OR矩阵的每一行中，预先写入用于产生后续微地址的微地址和数量的区域，以便分别获得关于微地址的信息和关于区域号的信息。 包含在微程序中的至少一个微指令将根据所获得的微地址从只读存储器中读出以执行相同的操作，同时在可编程逻辑阵列中产生后续微程序的微地址。 即，并行执行微程序程序的执行和后续微程序程序的第一地址的产生，从而可以实现微程序的有效执行，而每个微指令不需要包括区域号信息。

公开(公告)号：US4860109A

公开(公告)日：1989-08-22

申请号：US137028

申请日：1987-12-23

申请人： Katsura Kawakami ,  Shigeo Shimazaki ,  Satoshi Takayama ,  Chika Onodera

发明人： Katsura Kawakami ,  Shigeo Shimazaki ,  Satoshi Takayama ,  Chika Onodera

IPC分类号： G06T1/60 ,  H04N1/387

CPC分类号： G06T1/60 ,  H04N1/3873

摘要： An image processing apparatus includes a memory having a first region and a second region. The first memory region holds original image data. A first calculation device calculates addresses of segments of the first memory region. A second calculation device calculates addresses of segments of the second memory region. The original image data are transferred from the first memory region to the second memory region in accordance with the calculated addresses of the segments of the first and second memory regions. The first calculation device and the second calculation device are mutually independent. The calculation of the addresses of the segments of the first memory region is performed simultaneously with the calculation of the addresses of the segments of the second memory region.

摘要翻译： 图像处理装置包括具有第一区域和第二区域的存储器。 第一存储区域保存原始图像数据。 第一计算装置计算第一存储器区域的段的地址。 第二计算装置计算第二存储器区域的段的地址。 根据计算出的第一和第二存储器区段的地址，将原始图像数据从第一存储器区域传送到第二存储器区域。 第一计算装置和第二计算装置是相互独立的。 第一存储器区段的地址的计算与第二存储器区段的地址的计算同时执行。