公开(公告)号：US20090085626A1

公开(公告)日：2009-04-02

申请号：US12232162

申请日：2008-09-11

申请人： Shigeyuki Ueno ,  Hiroyuki Nakajima

发明人： Shigeyuki Ueno ,  Hiroyuki Nakajima

IPC分类号： H03K3/289

CPC分类号： G06F13/362 ,  G06F15/7807

摘要： When a master circuit is in an inactive state, a slave circuit assigned to the master circuit is not used. Accordingly, the use efficiency of system recourses is decreased. To solve the above problem, a semiconductor integrated circuit reassigns a M2 region of a slave circuit, previously assigned to a first master circuit, to a second master circuit. That is to say, the M2 region of the slave circuit previously assigned to the first master circuit is reassigned to the second master circuit based on the operational status of the first master circuit. This improves the use efficiency of system resources of the semiconductor integrated circuit.

摘要翻译： 当主电路处于非活动状态时，不使用分配给主电路的从电路。 因此，系统资源的使用效率降低。 为了解决上述问题，半导体集成电路将先前分配给第一主电路的从电路的M2区域重新分配给第二主电路。 也就是说，先前分配给第一主电路的从属电路的M2区域基于第一主电路的操作状态被重新分配给第二主电路。 这提高了半导体集成电路的系统资源的使用效率。

公开(公告)号：US20130013831A1

公开(公告)日：2013-01-10

申请号：US13619403

申请日：2012-09-14

申请人： Shigeyuki UENO ,  Hiroyuki Nakajima

发明人： Shigeyuki UENO ,  Hiroyuki Nakajima

IPC分类号： G06F13/40

CPC分类号： G06F13/362 ,  G06F15/7807

摘要： A semiconductor integrated circuit, including a first master circuit, a second master circuit, a first slave circuit assigned to the first master circuit, and determines that an access request signal is sent from the first master circuit when an identification information is a first value, a first bus coupled to the first master circuit, the second master circuit, and the first slave circuit, a bus controller is configured to transmit the access request signal to the first slave circuit via the first bus, a system controller directs the bus controller to substitute the first value for a second value on the identification information of the access request signal received from the second master circuit when the first master circuit is in the deactivated state.

摘要翻译： 一种半导体集成电路，包括第一主电路，第二主电路，分配给第一主电路的第一从电路，并且当识别信息是第一值时，确定从第一主电路发送访问请求信号， 耦合到第一主电路，第二主电路和第一从电路的第一总线，总线控制器被配置为经由第一总线将访问请求信号发送到第一从电路，系统控制器将总线控制器引导到 当第一主电路处于去激活状态时，将从第二主电路接收的接入请求信号的识别信息替换第二值作为第二值。

公开(公告)号：US20080072212A1

公开(公告)日：2008-03-20

申请号：US11898537

申请日：2007-09-13

申请人： Shigeyuki Ueno

发明人： Shigeyuki Ueno

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F11/3648

摘要： A semiconductor integrated circuit has a CPU executing a target program to be debugged, a peripheral circuit generating an internal signal in response to an operation of the CPU, and a monitor unit storing the internal signal of the peripheral circuit in response to a first status signal from the CPU executing the target program.

摘要翻译： 半导体集成电路具有执行要调试的目标程序的CPU，响应于CPU的操作而产生内部信号的外围电路，以及响应于第一状态信号存储外围电路的内部信号的监视单元 从CPU执行目标程序。

公开(公告)号：US07636870B2

公开(公告)日：2009-12-22

申请号：US11586505

申请日：2006-10-26

申请人： Shigeyuki Ueno

发明人： Shigeyuki Ueno

IPC分类号： G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3632

摘要： To provide a debugging system, debugging method, and a semiconductor integrated circuit device capable of collecting debug-target information with accuracy and improving debug efficiency. A semiconductor integrated circuit device according to an embodiment of the present invention includes: subsystems; a break detecting unit detecting that a program execution of a CPU core in one subsystem satisfies a predetermined break condition; and a break selecting unit stopping operations of one selected from the subsystems in accordance with the detection result of the break detecting unit.

摘要翻译： 提供调试系统，调试方法和能够准确收集调试目标信息并提高调试效率的半导体集成电路器件。 根据本发明实施例的半导体集成电路器件包括：子系统; 检测一个子系统中的CPU核的程序执行满足预定的中断条件的中断检测单元; 以及中断选择单元，根据断点检测单元的检测结果停止从子系统中选择的一个操作。

公开(公告)号：US08621262B2

公开(公告)日：2013-12-31

申请号：US13619403

申请日：2012-09-14

申请人： Shigeyuki Ueno ,  Hiroyuki Nakajima

发明人： Shigeyuki Ueno ,  Hiroyuki Nakajima

IPC分类号： G06F11/00

CPC分类号： G06F13/362 ,  G06F15/7807

摘要： A semiconductor integrated circuit, including a first master circuit, a second master circuit, a first slave circuit assigned to the first master circuit, and determines that an access request signal is sent from the first master circuit when an identification information is a first value, a first bus coupled to the first master circuit, the second master circuit, and the first slave circuit, a bus controller is configured to transmit the access request signal to the first slave circuit via the first bus, a system controller directs the bus controller to substitute the first value for a second value on the identification information of the access request signal received from the second master circuit when the first master circuit is in the deactivated state.

摘要翻译： 一种半导体集成电路，包括第一主电路，第二主电路，分配给第一主电路的第一从电路，并且当识别信息是第一值时，确定从第一主电路发送访问请求信号， 耦合到第一主电路，第二主电路和第一从电路的第一总线，总线控制器被配置为经由第一总线将访问请求信号发送到第一从电路，系统控制器将总线控制器引导到 当第一主电路处于去激活状态时，将从第二主电路接收的接入请求信号的识别信息替换第二值作为第二值。

公开(公告)号：US20070101198A1

公开(公告)日：2007-05-03

申请号：US11586505

申请日：2006-10-26

申请人： Shigeyuki Ueno

发明人： Shigeyuki Ueno

IPC分类号： G06F11/00

CPC分类号： G06F11/3636 ,  G06F11/3632

摘要： To provide a debugging system, debugging method, and a semiconductor integrated circuit device capable of collecting debug-target information with accuracy and improving debug efficiency. A semiconductor integrated circuit device according to an embodiment of the present invention includes: subsystems; a break detecting unit detecting that a program execution of a CPU core in one subsystem satisfies a predetermined break condition; and a break selecting unit stopping operations of one selected from the subsystems in accordance with the detection result of the break detecting unit.

摘要翻译： 提供调试系统，调试方法和能够准确收集调试目标信息并提高调试效率的半导体集成电路器件。 根据本发明实施例的半导体集成电路器件包括：子系统; 检测一个子系统中的CPU核的程序执行满足预定的中断条件的中断检测单元; 以及中断选择单元，根据断点检测单元的检测结果停止从子系统中选择的一个操作。