Abstract:
A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.
Abstract:
Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.
Abstract:
Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.