Synchronous clock multiplexing and output-enable
    1.
    发明授权
    Synchronous clock multiplexing and output-enable 有权
    同步时钟复用和输出使能

    公开(公告)号:US08054103B1

    公开(公告)日:2011-11-08

    申请号:US12909837

    申请日:2010-10-22

    CPC classification number: G06F1/12

    Abstract: A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

    Abstract translation: 用于时钟复用和输出使能的同步电路使用一对逻辑门和输出块来实现。 选择信号并使具有相应逻辑感的信号被提供作为逻辑门对的输入,这些逻辑门产生相应的逻辑输出。 输出块包含由相应输入信号计时的同步器,并接收逻辑输出作为输入。 输出块提供所选输入信号中的一个作为输出,所选择的输入信号的提供以同步的方式完成。 同时执行启用和禁用输出。

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