公开(公告)号：US06700050B2

公开(公告)日：2004-03-02

申请号：US10081449

申请日：2002-02-21

申请人： Shinya Sakurada ,  Akira Iizuka ,  Harumichi Hotta ,  Shizuhiko Kawai ,  Kozo Tokuda ,  Masaki Kudo

发明人： Shinya Sakurada ,  Akira Iizuka ,  Harumichi Hotta ,  Shizuhiko Kawai ,  Kozo Tokuda ,  Masaki Kudo

IPC分类号： G10H118

CPC分类号： G10H1/0058 ,  G10H2240/311

摘要： A bus system interconnects a plurality of devices of various categories constituting an electronic music instrument apparatus for exchanging signals among the devices having unique addresses. The bus system has a serial clock line for transmission of a clock signal, and a serial data line for transfer of a data signal from a source device to a destination device in synchronization with the clock signal. The source device operates as a master to commence a communicating session such as to send the clock signal to the serial clock line and to send the data signal to the serial data line in synchronization with the clock signal. The destination device operates as a slave so as to receive the data signal based on the clock signal. The source device formulates the data signal containing a unique address specifying the destination device such that the destination device can receive the data signal exclusively from the source device. The unique address contains category information designating a category to which the destination device belongs and a sub-address specifying the destination device in the designated category.

摘要翻译： 总线系统将构成用于在具有唯一地址的设备之间交换信号的电子乐器装置的各种类型的设备互连。 总线系统具有用于传输时钟信号的串行时钟线和用于与时钟信号同步地将数据信号从源设备传送到目的地设备的串行数据线。 源设备作为主机操作以开始通信会话，例如将时钟信号发送到串行时钟线并且将数据信号与时钟信号同步地发送到串行数据线。 目的地设备作为从机操作，以便基于时钟信号接收数据信号。 源设备制定包含指定目的地设备的唯一地址的数据信号，使得目的地设备可以从源设备专门接收数据信号。 唯一地址包含指定目的地设备所属的类别的类别信息和指定指定类别中的目的地设备的子地址。

公开(公告)号：US5804750A

公开(公告)日：1998-09-08

申请号：US763720

申请日：1996-12-13

申请人： Tokio Shirakawa ,  Masaki Kudo ,  Shizuhiko Kawai

发明人： Tokio Shirakawa ,  Masaki Kudo ,  Shizuhiko Kawai

IPC分类号： G10H1/18 ,  G10H1/02 ,  G10H7/00

CPC分类号： G10H7/006 ,  G10H7/004

摘要： A control circuit is integrated in a semiconductor chip for controlling operation of an electronic musical instrument according to a custom program stored in an external memory so as to generate a musical tone. In the control circuit, an internal memory is formed in the semiconductor chip separately from the external memory for permanently storing a common program which is dedicated to synthesis of the musical tone while the custom program stored in the external memory is customized for the operation of the electronic musical instrument. A tone synthesizer is formed in the same semiconductor chip for synthesizing -,he musical tone when the common program is executed. A central processor is formed in the same semiconductor chip integrally with the tone synthesizer and the internal memory for executing the custom program to control the operation of the electronic musical instrument and for executing the common program to effectuate the synthesis of the musical tone to generate the same sequentially in response to the operation of the electronic musical instrument.

摘要翻译： 控制电路集成在半导体芯片中，用于根据存储在外部存储器中的定制程序控制电子乐器的操作，以便产生乐音。 在控制电路中，与外部存储器分离地形成在半导体芯片中的内部存储器，用于永久存储专用于音乐合成的公共程序，同时存储在外部存储器中的定制程序被定制用于 电子乐器。 音频合成器形成在同一半导体芯片中，用于合成 - 当执行公共节目时，它是音调。 中央处理器与与音调合成器和内部存储器整体形成在同一半导体芯片中，用于执行定制程序以控制电子乐器的操作并执行公共程序以实现乐音的合成以产生 响应于电子乐器的操作顺序地相同。

公开(公告)号：US5804749A

公开(公告)日：1998-09-08

申请号：US773200

申请日：1996-12-24

申请人： Tokio Shirakawa ,  Masaki Kudo ,  Shizuhiko Kawai

发明人： Tokio Shirakawa ,  Masaki Kudo ,  Shizuhiko Kawai

IPC分类号： G10H7/00 ,  G10H7/02 ,  G11C7/00 ,  G11C7/16 ,  H03M7/00

CPC分类号： G11C7/00 ,  G10H7/002 ,  G10H7/02 ,  G11C7/16 ,  G11C2207/16

摘要： In a sound source apparatus, a central processing unit is integrated in a semiconductor chip and operates in response to a primary operating clock signal for creating a control message. A tone generating unit is integrated in the same semiconductor chip and operates in response to a secondary operating clock signal for generating a musical tone according to the control message. A master clock generator generates a master clock signal having a desired frequency selected from a plurality of frequencies. A mode changer designates one of a first mode and a second mode corresponding to different operating speeds. A clock generator is provided for variably frequency-dividing the master clock signal to generate the primary operating clock signal and the secondary operating clock signal. The clock generator is responsive to the mode changer for changing a frequency ratio of the primary operating clock signal to the secondary operating clock signal between the first mode and the second mode. An external memory is provided separately from the semiconductor chip for storing information required for generation of the musical tone. A memory controller is provided for allotting a primary time slot to the central processing unit and a secondary time slot to the tone generating unit such as to optimize access to the external memory shared by the central processing unit and the tone generating unit. A cache memory is provided to speed up operation of the central processing unit.

摘要翻译： 在声源装置中，中央处理单元被集成在半导体芯片中，并且响应于用于产生控制消息的主操作时钟信号而操作。 乐音产生单元集成在相同的半导体芯片中，并且响应于辅助操作时钟信号而操作，用于根据控制消息产生乐音。 主时钟发生器产生具有从多个频率选择的期望频率的主时钟信号。 模式转换器指定对应于不同操作速度的第一模式和第二模式之一。 提供时钟发生器用于可变地分频主时钟信号以产生主操作时钟信号和辅助操作时钟信号。 时钟发生器响应于模式转换器，用于在第一模式和第二模式之间改变初级工作时钟信号与辅助操作时钟信号的频率比。 与半导体芯片分离地提供外部存储器，用于存储产生音调所需的信息。 提供存储器控制器，用于将主时隙分配给中央处理单元，并将次要时隙分配给音调生成单元，以便优化对由中央处理单元和乐音发生单元共享的外部存储器的访问。 提供高速缓冲存储器以加速中央处理单元的操作。