公开(公告)号：US06765843B2

公开(公告)日：2004-07-20

申请号：US10369562

申请日：2003-02-21

申请人： Kaoru Mori ,  Shuji Mabuchi

发明人： Kaoru Mori ,  Shuji Mabuchi

IPC分类号： G11C800

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C8/12

摘要： A semiconductor memory device includes a plurality of memory blocks, a plurality of data buses provided for the respective memory blocks, a plurality of buffer circuits which are provided for the respective memory blocks, and relay data of the data buses to connect the data buses in series, a block activation circuit which generates block selection signals corresponding to the respective memory blocks, and asserts one of the block selection signals to selectively activate one of the memory blocks, and a plurality of buffer control circuits which are provided for the respective memory blocks, one of the buffer control circuits activating a corresponding one of the buffer circuits in response to assertion of a corresponding one of the block selection signals or in response to activation of one of the buffer circuits at an adjacent one of the memory blocks that is located upstream along the data buses.

摘要翻译： 半导体存储器件包括多个存储块，为各个存储块提供的多个数据总线，为各个存储块提供的多个缓冲电路，以及数据总线的中继数据，以连接数据总线 系列，块激活电路，其生成对应于各个存储块的块选择信号，并且断言块选择信号之一以选择性地激活其中一个存储块;以及多个缓冲器控制电路，用于各个存储块 缓冲器控制电路中的一个响应于块选择信号中对应的一个块的选择而激活对应的一个缓冲器电路，或响应于位于相邻的一个存储器块中的一个缓冲器电路的激活 沿数据总线上游。