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公开(公告)号：US5749091A
公开(公告)日：1998-05-05
申请号：US355093
申请日：1994-12-13
申请人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
发明人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
CPC分类号： G11C29/74 , G06F11/1407 , G06F12/0804 , G06F12/0891 , G06F11/00
摘要： A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.
摘要翻译： 一种高速执行高速缓存清除操作并具有实时特性的容错计算机。 处理器模块301配备有高速缓冲存储器，使得高速缓冲存储器内的更新的高速缓存块的入口地址被存储在堆栈中。 当由于定时器等而导致的恢复点设置条件被满足时，高速缓冲存储器仅针对堆叠中的输入地址进行。 存储器模块303具有在相同的存储物理空间中翻倍的布置，并且配备有用于临时存储所传送的高速缓存块的缓冲存储器，从而高速缓存块被同时传送到一对缓冲存储器。
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2.发明授权System for performing cache flush transactions from interconnected processor modules to paired memory modules 失效用于从互连的处理器模块到配对的存储器模块执行缓存刷新事务的系统
公开(公告)号：US5829030A
公开(公告)日：1998-10-27
申请号：US992757
申请日：1997-12-17
申请人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
发明人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
CPC分类号： G11C29/74 , G06F11/1407 , G06F12/0804 , G06F12/0891 , G06F11/00
摘要： A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.
摘要翻译： 一种高速执行高速缓存清除操作并具有实时特性的容错计算机。 处理器模块301配备有高速缓冲存储器，使得高速缓冲存储器内的更新的高速缓存块的入口地址被存储在堆栈中。 当由于定时器等而导致的恢复点设置条件被满足时，高速缓冲存储器仅针对堆叠中的输入地址进行。 存储器模块303具有在相同的存储物理空间中翻倍的布置，并且配备有用于临时存储所传送的高速缓存块的缓冲存储器，从而高速缓存块被同时传送到一对缓冲存储器。
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3.发明授权Cache controller fault tolerant computer and data transfer system setting recovery points 失效缓存控制器容错计算机和数据传输系统设置恢复点
公开(公告)号：US06070232A
公开(公告)日：2000-05-30
申请号：US948430
申请日：1997-10-10
申请人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
发明人： Hitoshi Ishida , Minoru Shiga , Toyohito Hatashita , Yuichi Tokunaga , Hiroyuki Fukuda , Shunyo Minesaki
CPC分类号： G11C29/74 , G06F11/1407 , G06F12/0804 , G06F12/0891 , G06F11/00
摘要： A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.
摘要翻译： 一种高速执行高速缓存清除操作并具有实时特性的容错计算机。 处理器模块配备有高速缓冲存储器，使得高速缓冲存储器内的更新的高速缓存块的入口地址被存储在堆栈中。 当由于定时器等而导致的恢复点设置条件被满足时，高速缓冲存储器仅针对堆叠中的输入地址进行。 存储器模块具有在相同存储物理空间中翻倍的布置，并且配备有用于临时存储所传送的高速缓存块的缓冲存储器，使得高速缓存块被同时传送到一对缓冲存储器。
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