公开(公告)号：US06834018B2

公开(公告)日：2004-12-21

申请号：US10291216

申请日：2002-11-08

申请人： Takeshi Okazawa ,  Shuuichi Tahara

发明人： Takeshi Okazawa ,  Shuuichi Tahara

IPC分类号： G11C702

CPC分类号： G11C11/16

摘要： A semiconductor memory device as claimed in the present invention has a reference cell, a first memory cell, a second memory cell located nearer the first memory cell than the reference cell and a data read circuit provided therein. The data read circuit identifies first data stored in the first memory cell based on a reference cell electrical state of the reference cell and a first electrical state of the first memory cell. Furthermore, the data read circuit identifies second data stored in the second memory cell based on the first electrical state of the first memory cell and a second electrical state of the second memory cell. The semiconductor memory device having such configuration is able to suppress influence of variation in electrical performance of memory cell and stably identify data stored in a memory cell.

摘要翻译： 本发明的半导体存储器件具有比参考单元更靠近第一存储单元的参考单元，第一存储单元，第二存储器单元和设置在其中的数据读取电路。 数据读取电路基于参考单元的参考单元电状态和第一存储单元的第一电状态来识别存储在第一存储器单元中的第一数据。 此外，数据读取电路基于第一存储单元的第一电状态和第二存储单元的第二电状态来识别存储在第二存储单元中的第二数据。 具有这种结构的半导体存储器件能够抑制存储单元的电气性能变化的影响，并且可以稳定地识别存储在存储单元中的数据。