公开(公告)号：US06834018B2

公开(公告)日：2004-12-21

申请号：US10291216

申请日：2002-11-08

申请人： Takeshi Okazawa ,  Shuuichi Tahara

发明人： Takeshi Okazawa ,  Shuuichi Tahara

IPC分类号： G11C702

CPC分类号： G11C11/16

摘要： A semiconductor memory device as claimed in the present invention has a reference cell, a first memory cell, a second memory cell located nearer the first memory cell than the reference cell and a data read circuit provided therein. The data read circuit identifies first data stored in the first memory cell based on a reference cell electrical state of the reference cell and a first electrical state of the first memory cell. Furthermore, the data read circuit identifies second data stored in the second memory cell based on the first electrical state of the first memory cell and a second electrical state of the second memory cell. The semiconductor memory device having such configuration is able to suppress influence of variation in electrical performance of memory cell and stably identify data stored in a memory cell.

摘要翻译： 本发明的半导体存储器件具有比参考单元更靠近第一存储单元的参考单元，第一存储单元，第二存储器单元和设置在其中的数据读取电路。 数据读取电路基于参考单元的参考单元电状态和第一存储单元的第一电状态来识别存储在第一存储器单元中的第一数据。 此外，数据读取电路基于第一存储单元的第一电状态和第二存储单元的第二电状态来识别存储在第二存储单元中的第二数据。 具有这种结构的半导体存储器件能够抑制存储单元的电气性能变化的影响，并且可以稳定地识别存储在存储单元中的数据。

公开(公告)号：US06477077B2

公开(公告)日：2002-11-05

申请号：US09911709

申请日：2001-07-25

申请人： Takeshi Okazawa

发明人： Takeshi Okazawa

IPC分类号： G11C1122

CPC分类号： G11C11/15

摘要： A non-volatile memory device has a plurality of row lines extending in a first direction, a plurality of column lines extending in a second direction differing from the first direction, the plurality of column lines and the plurality of row lines forming a wiring matrix, a plurality of memory cells disposed at intersection points between the plurality of row lines and the plurality of column lines of the wiring matrix, each memory cell being formed by two ferromagnetic thin films and an insulation film therebetween, a wiring selection means for selecting at least one row line from the plurality of row lines and selecting at least one column line from the plurality of column lines, and a potential applying means for causing a prescribed current to flow in the selected row lines and column lines and applying to the row lines and column lines other than the selected row lines and column lines a prescribed potential which is not a ground potential.

摘要翻译： 非易失性存储器件具有沿第一方向延伸的多条行线，沿与第一方向不同的第二方向延伸的多条列线，多条列线和多条行线形成布线矩阵， 多个存储单元，其设置在所述布线矩阵的多个列线与所述多个列线之间的交点处，每个存储单元由两个铁磁性薄膜及其间的绝缘膜形成，布线选择装置，至少选择 从所述多行行中选择一列，并从所述多列列中选择至少一列;以及电位施加装置，用于使所述规定电流在所选择的行行和列线中流动并施加到所述行线和 列线除了所选择的行线和列线之外的不是地电位的规定电位。

公开(公告)号：US5972750A

公开(公告)日：1999-10-26

申请号：US16952

申请日：1998-02-02

申请人： Hiroki Shirai ,  Taishi Kubota ,  Ichiro Honma ,  Hirohito Watanabe ,  Haruhiko Ono ,  Takeshi Okazawa

发明人： Hiroki Shirai ,  Taishi Kubota ,  Ichiro Honma ,  Hirohito Watanabe ,  Haruhiko Ono ,  Takeshi Okazawa

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/72

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883 ,  Y10S257/90

摘要： There are disclosed a nonvolatile semiconductor memory device, which is capable of maintaining a high capacitance ratio even when a memory cell is formed in a micronized size without increasing the number of manufacturing steps, and its manufacturing method. In a flash memory having buried diffusion layer type cells, a source region and drain regions and are formed in self alignment with a polycrystalline film pattern which has a polycrystalline silicon film having projecting and recessing parts in its upper surface.

摘要翻译： 公开了一种非易失性半导体存储器件，即使在不增加制造步骤数量的情况下，即使在微型化尺寸形成存储单元时也能够保持高电容比及其制造方法。 在具有掩埋扩散层型电池的闪速存储器中，源极区域和漏极区域形成为与其上表面具有突出和凹陷部分的多晶硅膜的多晶膜图案自对准地形成。

公开(公告)号：US5371704A

公开(公告)日：1994-12-06

申请号：US157568

申请日：1993-11-26

申请人： Takeshi Okazawa

发明人： Takeshi Okazawa

IPC分类号： G11C17/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： H01L29/66825 ,  H01L29/42336 ,  H01L29/7885 ,  H01L27/115

摘要： A groove is formed in a semiconductor layer, and a source region is formed at a part of the groove within the semiconductor layer. A control gate is buried via a first insulating layer within the groove. A floating gate is formed via a second insulating layer on the control gate. The floating gate extends over the first insulating layer. A drain region is formed within the semiconductor layer apart from the groove.

摘要翻译： 在半导体层中形成沟槽，在半导体层内的沟槽的一部分形成源极区域。 控制栅极通过沟槽内的第一绝缘层埋设。 通过控制栅极上的第二绝缘层形成浮栅。 浮栅在第一绝缘层上延伸。 漏极区域形成在半导体层中，与沟槽分开。

公开(公告)号：US4700212A

公开(公告)日：1987-10-13

申请号：US839450

申请日：1986-03-03

申请人： Takeshi Okazawa

发明人： Takeshi Okazawa

IPC分类号： H01L29/78 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L27/02

CPC分类号： H01L23/5222 ,  H01L21/74 ,  H01L21/76202 ,  H01L27/088 ,  H01L2924/0002

摘要： The present invention relates to a semiconductor integrated circuit device of high degree of integration. A first element region and a second element region are provided with a field insulating film interposed therebetween on a semiconductor substrate of one conductivity type. Impurity regions of one conductivity type having a high impurity concentration are separately formed in the substrate at locations of the first and second element regions, respectively. The respective impurity regions are wider that the respective element regions, and extends under end portions of the field insulating film but not under the center portion thereof. A wiring layer is provided on the center portion of the field insulating film beneath which no impurity region exists. The element regions are isolated from each other by a predetermined threshold voltage determined by the end portions of the field insulating film and by the underlying high impurity regions. Further, parasitic capacity can be reduced between the wiring layer and the semiconductor substrate since no impurity region having high concentration exists under the wiring layer.

摘要翻译： 本发明涉及高集成度的半导体集成电路器件。 第一元件区域和第二元件区域在一个导电类型的半导体衬底上设置有介于它们之间的场绝缘膜。 具有高杂质浓度的一种导电类型的杂质区域分别在第一和第二元件区域的位置处分别形成在衬底中。 各个杂质区域比各个元件区域宽，并且在场绝缘膜的端部处延伸，但不在其中心部分下方。 在不存在杂质区域的场绝缘膜的中心部分设置布线层。 元件区域通过由绝缘膜的端部和下面的高杂质区域确定的预定阈值电压彼此隔离。 此外，由于在布线层下面不存在具有高浓度的杂质区域，所以在布线层和半导体基板之间可以减小寄生电容。

公开(公告)号：US20050064157A1

公开(公告)日：2005-03-24

申请号：US10979428

申请日：2004-11-02

申请人： Takeshi Okazawa ,  Katsumi Suemitsu

发明人： Takeshi Okazawa ,  Katsumi Suemitsu

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/56 ,  H01F10/32 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  B32B7/06

CPC分类号： G11C11/5607 ,  G11C11/15 ,  G11C11/161 ,  Y10T428/2486

摘要： A magnetic memory according to the present invention comprises: a single magnetic memory cell having at least first to third magnetic layers, a first tunnel insulating layer between the first and second magnetic layers and a second tunnel insulating layer between the second and third magnetic layers. The resistance between the first and third magnetic layers when magnetization of the first and second magnetic layers are in opposite directions is different from the resistance between the second and third magnetic layers when magnetization of the second and third magnetic layers are in opposite directions. Multiple data are therefore stored into the memory cell.

摘要翻译： 根据本发明的磁存储器包括：具有至少第一至第三磁性层的单个磁存储单元，在第一和第二磁性层之间的第一隧道绝缘层以及第二和第三磁性层之间的第二隧道绝缘层。 当第一和第二磁性层的磁化方向处于相反方向时，第一和第三磁性层之间的电阻不同于当第二和第三磁性层的磁化方向相反时第二和第三磁性层之间的电阻。 因此，多个数据被存储到存储单元中。

公开(公告)号：US06812537B2

公开(公告)日：2004-11-02

申请号：US10141602

申请日：2002-05-08

申请人： Takeshi Okazawa ,  Katsumi Suemitsu

发明人： Takeshi Okazawa ,  Katsumi Suemitsu

IPC分类号： H01L2982

CPC分类号： G11C11/5607 ,  G11C11/15 ,  Y10T428/2486

摘要： A magnetic memory according to the present invention comprises: a single magnetic memory cell having at least first to third magnetic layers, a first tunnel insulating layer between the first and second magnetic layers and a second tunnel insulating layer between the second and third magnetic layers. The resistance between the first and third magnetic layers when magnetization of the first and second magnetic layers are in opposite directions is different from the resistance between the second and third magnetic layers when magnetization of the second and third magnetic layers are in opposite directions. Multiple data are therefore stored into the memory cell.

摘要翻译： 根据本发明的磁存储器包括：具有至少第一至第三磁性层的单个磁存储单元，在第一和第二磁性层之间的第一隧道绝缘层以及第二和第三磁性层之间的第二隧道绝缘层。 当第一和第二磁性层的磁化方向处于相反方向时，第一和第三磁性层之间的电阻不同于当第二和第三磁性层的磁化方向相反时第二和第三磁性层之间的电阻。 因此，多个数据被存储到存储单元中。

公开(公告)号：US5309402A

公开(公告)日：1994-05-03

申请号：US835357

申请日：1992-02-14

申请人： Takeshi Okazawa

发明人： Takeshi Okazawa

IPC分类号： G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  G11C11/40

CPC分类号： H01L27/11517 ,  G11C16/16 ,  H01L27/115

摘要： A flash EEPROM with sector erasure, carries out the erasure by applying a negative voltage to a selected word line through an N-channel MOS transistor. P-channel MOS transistors are respectively inserted between row decoder level shifters and each of their respective word lines to which they are respectively connected. The turning-on and -off of the respective word lines and first level shifters is controlled by the turning-on and -off of the associated P-channel MOS transistor. An erase voltage is applied to one end of the source/drain path of the respective N-channel MOS transistor of the selected cord line, the other end to the respective word lines. The turning-on and -off of the N-channel MOS transistor is synchronized with the turning-on and -off of the P-channel MOS transistor connected to the same word line. The P-channel MOS transistor is formed on an N well biased to, for example, 5 V and the N-channel MOS transistor is formed on a P well biased to, for example, the erase voltage. The P well is formed on the surface of the N well.

摘要翻译： 具有扇区擦除的快闪EEPROM通过通过N沟道MOS晶体管对所选字线施加负电压来执行擦除。 P沟道MOS晶体管分别插入在行解码器电平移位器和它们各自连接的各自的字线之间。 各个字线和第一电平移位器的导通和关断由相关的P沟道MOS晶体管的导通和关断来控制。 擦除电压被施加到所选择的线路的各个N沟道MOS晶体管的源极/漏极路径的一端，另一端被施加到各个字线。 N沟道MOS晶体管的导通和关断与连接到同一字线的P沟道MOS晶体管的导通和关断同步。 P沟道MOS晶体管形成在N阱上，例如被偏压到5V，并且N沟道MOS晶体管形成在P偏置到例如擦除电压的P上。 P井形成在N井的表面上。

公开(公告)号：US5295107A

公开(公告)日：1994-03-15

申请号：US24074

申请日：1993-03-01

申请人： Takeshi Okazawa ,  Ken-Ichi Oyama ,  Hiroki Shirai

发明人： Takeshi Okazawa ,  Ken-Ichi Oyama ,  Hiroki Shirai

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3409 ,  G11C16/16

摘要： A method of controlling the nonvolatile memory device comprising making over-erasing simultaneously a set of EEPROM elements and then setting simultaneously the threshold voltages of said set of EEPROM elements back to the specified threshold-voltage values. The over-erasing is accomplished by applying a first pulse between the source and the control gate to induce the first FN current across the gate insulating film. The setting-back is accomplished by applying a second pulse between the well and the control gate to induce the second FN current flowing reversely to the first FN current.

摘要翻译： 一种控制非易失性存储器件的方法，包括同时进行一组EEPROM元件的过度擦除，然后同时将所述EEPROM元件组的阈值电压恢复到指定的阈值电压值。 通过在源极和控制栅极之间施加第一脉冲以引导跨越栅极绝缘膜的第一FN电流来实现过擦除。 通过在阱和控制栅之间施加第二脉冲以引起与第一FN电流相反流动的第二FN电流来实现回调。

公开(公告)号：US07009876B2

公开(公告)日：2006-03-07

申请号：US10690287

申请日：2003-10-21

申请人： Takeshi Okazawa

发明人： Takeshi Okazawa

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： In an MRAM having main and sub-structures, selecting transistors are arranged so as to meet the arrangement order of main word lines, sub-word lines and the selecting transistors. The selecting transistor is driven to cause a snap back phenomenon to occur. As a result, data can be written to a memory cell using a substrate current, not a channel current. Moreover, a data may be written into a selected memory cell by discharge the charge which is charged in the main and sub word lines corresponding to the memory cell.

摘要翻译： 在具有主子结构和子结构的MRAM中，选择晶体管被配置成满足主字线，子字线和选择晶体管的排列顺序。 驱动选择晶体管，引起闪回现象。 结果，可以使用衬底电流而不是通道电流将数据写入存储器单元。 此外，可以通过放电在与存储单元对应的主字线和子字线中充电的电荷来将数据写入选择的存储单元。