公开(公告)号：US06326672B1

公开(公告)日：2001-12-04

申请号：US09560704

申请日：2000-04-27

Applicant: Siang Ping Kwok

Inventor： Siang Ping Kwok

IPC: H01L2900

CPC classification number: H01L21/76205

Abstract: In one aspect, the invention encompasses a LOCOS process. A pad oxide layer is provided over a silicon-comprising substrate. A silicon nitride layer is provided over the pad oxide layer and patterned with the pad oxide layer to form masking blocks. The patterning exposes portions of the silicon-comprising substrate between the masking blocks. The masking blocks comprise sidewalls. Polysilicon is formed along the sidewalls of the masking blocks. Subsequently, the silicon-comprising substrate and polysilicon are oxidized to form field oxide regions proximate the masking blocks. In another aspect, the invention encompasses a semiconductive material structure. Such structure includes a semiconductive material substrate and at least one composite block over the semiconductive material substrate. The composite block comprises a layer of silicon dioxide and a layer of silicon nitride over the layer of silicon dioxide. The silicon nitride and silicon dioxide have coextensive opposing sidewalls. The structure also comprises polysilicon projections along the coextensive silicon nitride and second dioxide sidewalls.

Abstract translation: 一方面，本发明包括LOCOS方法。 衬垫氧化物层设置在含硅衬底上。 在衬垫氧化物层上提供氮化硅层，并用衬垫氧化物层图案化以形成掩模块。 图案化使掩模块之间的含硅衬底的部分暴露。 掩模块包括侧壁。 多晶硅沿掩蔽块的侧壁形成。 随后，将含硅衬底和多晶硅氧化以形成靠近掩模块的场氧化物区域。 在另一方面，本发明包括半导体材料结构。 这种结构包括半导体材料衬底和半导体材料衬底上的至少一个复合块。 复合块包括二氧化硅层和二氧化硅层上的氮化硅层。 氮化硅和二氧化硅具有共同相反的侧壁。 该结构还包括沿共同的氮化硅和二氧化硅侧壁的多晶硅突起。

公开(公告)号：US06872655B2

公开(公告)日：2005-03-29

申请号：US10358059

申请日：2003-02-04

Applicant: Pushpa Mahalingam ,  Robert Hung Nguyen ,  Philipp Steinmann ,  Eric W. Beach ,  Siang Ping Kwok

Inventor： Pushpa Mahalingam ,  Robert Hung Nguyen ,  Philipp Steinmann ,  Eric W. Beach ,  Siang Ping Kwok

IPC: H01C7/00 ,  H01L21/02 ,  H01L21/4763

CPC classification number: H01L28/24 ,  H01C7/006

Abstract: A thin film resistor structure (75) is formed on a dielectric layer (60). A capping layer (90) is formed above said thin film resistor structure (75) and vias (110) are formed in the capping layer (90) using a two step etching process comprising of a dry etch process and a wet etch process. Conductive layers (120) are formed in the vias and form electrical contacts to the thin film resistor structure (75).

Abstract translation: 在电介质层（60）上形成薄膜电阻结构（75）。 在所述薄膜电阻器结构（75）上方形成覆盖层（90），并且使用包括干法蚀刻工艺和湿蚀刻工艺的两步蚀刻工艺在覆盖层（90）中形成通孔（110）。 导电层（120）形成在通孔中并与薄膜电阻器结构（75）形成电接触。

公开(公告)号：US06429087B1

公开(公告)日：2002-08-06

申请号：US09386537

申请日：1999-08-30

Applicant: Siang Ping Kwok ,  William F. Richardson

Inventor： Siang Ping Kwok ,  William F. Richardson

IPC: H01L2120

Abstract: In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material. In another aspect, the invention encompasses a capacitor construction.

公开(公告)号：US06306726B1

公开(公告)日：2001-10-23

申请号：US09385698

申请日：1999-08-30

Applicant: Siang Ping Kwok

Inventor： Siang Ping Kwok

IPC: H01L2176

CPC classification number: H01L21/76205

Abstract: In one aspect, the invention encompasses a LOCOS process. A pad oxide layer is provided over a silicon-comprising substrate. A silicon nitride layer is provided over the pad oxide layer and patterned with the pad oxide layer to form masking blocks. The patterning exposes portions of the silicon-comprising substrate between the masking blocks. The masking blocks comprise sidewalls. Polysilicon is formed along the sidewalls of the masking blocks. Subsequently, the silicon-comprising substrate and polysilicon are oxidized to form field oxide regions proximate the masking blocks. In another aspect, the invention encompasses a semiconductive material structure. Such structure includes a semiconductive material substrate and at least one composite block over the semiconductive material substrate. The composite block comprises a layer of silicon dioxide and a layer of silicon nitride over the layer of silicon dioxide. The silicon nitride and silicon dioxide have coextensive opposing sidewalls. The structure also comprises polysilicon projections along the coextensive silicon nitride and second dioxide sidewalls.

Abstract translation: 一方面，本发明包括LOCOS方法。 衬垫氧化物层设置在含硅衬底上。 在衬垫氧化物层上提供氮化硅层，并用衬垫氧化物层图案化以形成掩模块。 图案化使掩模块之间的含硅衬底的部分暴露。 掩模块包括侧壁。 多晶硅沿掩蔽块的侧壁形成。 随后，将含硅衬底和多晶硅氧化以形成靠近掩模块的场氧化物区域。 在另一方面，本发明包括半导体材料结构。 这种结构包括半导体材料衬底和半导体材料衬底上的至少一个复合块。 复合块包括二氧化硅层和二氧化硅层上的氮化硅层。 氮化硅和二氧化硅具有共同相反的侧壁。 该结构还包括沿共同的氮化硅和二氧化硅侧壁的多晶硅突起。

公开(公告)号：US4245230A

公开(公告)日：1981-01-13

申请号：US79854

申请日：1979-09-28

Applicant: Siang-Ping Kwok ,  Glenn O. Ladd, Jr.

Inventor： Siang-Ping Kwok ,  Glenn O. Ladd, Jr.

IPC: H01L29/47 ,  H01L29/78 ,  H01L29/812 ,  H01L29/64 ,  H01L29/80

CPC classification number: H01L29/7839 ,  H01L29/475 ,  H01L29/812

Abstract: A Schottky barrier resistive gate switch which may be utilized for microwave switching. First and second metallizations which serve as signal inputs overlie a semiconductive substrate, making contact with a doped region thereof. A gate of high resistivity material which forms a Schottky barrier with the substrate is positioned between the metallizations. The doped region defines a channel, the conductivity of which is adjusted by the regulation of the Schottky depletion region formed therein.

Abstract translation: 可用于微波切换的肖特基势垒栅极开关。 用作信号输入的第一和第二金属化层叠在半导电基板上，与其掺杂区域接触。 与衬底形成肖特基势垒的高电阻率材料的栅极位于金属化之间。 掺杂区域限定通道，其通过其中形成的肖特基耗尽区的调节来调节其电导率。

公开(公告)号：US07005361B2

公开(公告)日：2006-02-28

申请号：US10875846

申请日：2004-06-24

Applicant: Siang Ping Kwok ,  Eric W. Beach ,  Philipp Steinmann

Inventor： Siang Ping Kwok ,  Eric W. Beach ,  Philipp Steinmann

IPC: H01L21/4763

CPC classification number: H01L27/0802 ,  H01L28/24

Abstract: In one embodiment, an integrated circuit includes a thin film resistor, which includes a resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the resistor material having an initial width determined by a width of the channel. The stencil structure has been adapted to receive a planarizing material that protects against reduction of the initial width of the resistor material during subsequent process steps for removing the stencil structure. A head mask overlays an end portion of the thin film resistor and a dielectric overlays the head mask, the dielectric defining a via formed in the dielectric above a portion of the head mask. A conductive material has been deposited in the via, coupled to the portion of the head mask and electrically connecting the thin film resistor to other components of the integrated circuit.

Abstract translation: 在一个实施例中，集成电路包括薄膜电阻器，薄膜电阻器包括已经沉积在由形成在衬底表面上的模板结构的相对的第一和第二部分限定的沟道内的衬底表面上的电阻材料，电阻器材料具有 由通道的宽度确定的初始宽度。 模板结构已经适于接收平面化材料，其在随后的去除模版结构的工艺步骤期间防止电阻材料的初始宽度的减小。 头部掩模覆盖薄膜电阻器的端部，并且电介质覆盖头部掩模，所述电介质限定在头罩中的一部分上形成在电介质中的通孔。 导电材料已经沉积在通孔中，耦合到头罩的部分并将薄膜电阻器电连接到集成电路的其它部件。

公开(公告)号：US06380008B2

公开(公告)日：2002-04-30

申请号：US09738001

申请日：2000-12-14

Applicant: Siang Ping Kwok ,  William F. Richardson ,  Dirk N. Anderson

Inventor： Siang Ping Kwok ,  William F. Richardson ,  Dirk N. Anderson

IPC: H01L2100

CPC classification number: H01L29/42376 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/4941

Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

Abstract translation: 薄膜导体边缘处的应力可以通过不重合的分层结构来减少，这样就可以利用边缘附近的拉伸到压缩特性应力极性，反之亦然，以避免器件的可靠性和性能问题。 通过使用非重合分层结构，可以实现来自不同层的破坏性应力干扰，以减少边缘处的应力或应力梯度。 本文公开的结构和方法可有利地用于许多集成电路和器件制造应用（包括门，字线和位线）中。

公开(公告)号：US06627938B2

公开(公告)日：2003-09-30

申请号：US09729130

申请日：2000-12-01

Applicant: Siang Ping Kwok ,  William F. Richardson

Inventor： Siang Ping Kwok ,  William F. Richardson

IPC: H01L27108

CPC classification number: H01L28/87 ,  H01L27/10855 ,  H01L28/91

Abstract: In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material. In another aspect, the invention encompasses a capacitor construction.

Abstract translation: 一方面，本发明包括形成电容器的方法。 质量在电气节点上形成。 在质量体内形成一个开口。 开口具有靠近节点的下部和在下部上方的上部。 下部比上部宽。 第一导电层形成在开口内并且沿着开口的周边。 在形成第一导电层之后，将质量的一部分从开口的上部旁边除去，而质量的另一部分留在开口的下部。 在第一导电层上形成电介质材料，并且在电介质材料上形成第二导电层。 第二导电层通过电介质材料与第一导电层分离。 在另一方面，本发明包括电容器结构。

公开(公告)号：US06373088B1

公开(公告)日：2002-04-16

申请号：US09096012

申请日：1998-06-10

Applicant: Siang Ping Kwok ,  William F. Richardson ,  Dirk N. Anderson

Inventor： Siang Ping Kwok ,  William F. Richardson ,  Dirk N. Anderson

IPC: H01L2100

Abstract: The stress at the edges of a thin film conductor can be reduced by noncoincident layered structures, which takes advantage of the characteristic stress polarity changing from tensile to compressive or vice versa in the edge vicinity in order to avoid device reliability and performance problems. By using noncoincident layered structures, destructive stress interference from different layers can be achieved to reduce the stress or stress gradient at the edge. The structures and methods disclosed herein can advantageously be used in many integrated circuit and device manufacturing applications (including gates, wordlines, and bitlines).

公开(公告)号：US06211037B1

公开(公告)日：2001-04-03

申请号：US09387661

申请日：1999-08-30

Applicant: Siang Ping Kwok

Inventor： Siang Ping Kwok

IPC: H01L2176

CPC classification number: H01L21/76202

Abstract: The invention includes a method of reducing stress during formation of field oxide by LOCOS. Field oxide is formed by oxidizing a silicon substrate, and fluorine is incorporated into the field oxide during the oxidizing. After the fluorine is incorporated into the field oxide, the field oxide is annealed at a temperature of at least about 1000° C.

Abstract translation: 本发明包括通过LOCOS在场氧化物形成期间降低应力的方法。 通过氧化硅衬底形成场氧化物，并且在氧化期间将氟结合到氧化物中。 在将氟掺入场氧化物中之后，场氧化物在至少约1000℃的温度下退火