公开(公告)号：US5691571A

公开(公告)日：1997-11-25

申请号：US578318

申请日：1995-12-26

申请人： Kazuyuki Hirose ,  Kuniko Kikuta

发明人： Kazuyuki Hirose ,  Kuniko Kikuta

IPC分类号： H01L23/485 ,  H01L23/532 ,  H01L29/45 ,  H01L23/48 ,  H01L29/46 ,  H01L29/52 ,  H01L29/64

CPC分类号： H01L23/485 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002

摘要： A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier metal is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.

摘要翻译： 半导体器件包括形成在半导体衬底上的至少一个孔。 在与孔中的半导体衬底接触的至少一个部分上形成阻挡金属。 金属互连由两层构成，包括形成在阻挡金属上的第一含Al金属膜和形成在第一含Al金属膜上的第二含Al金属膜，其熔点低于 第一含Al金属膜。

公开(公告)号：US5461261A

公开(公告)日：1995-10-24

申请号：US358979

申请日：1994-12-19

申请人： Masanori Nishiguchi

发明人： Masanori Nishiguchi

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62 ,  H01L29/64

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1358 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014

摘要： The semiconductor chip is provided with bumps each formed by alternately building up two types of metal materials capable of forming an eutectic alloy, and, therefore, an eutectic alloy reaction takes place at each boundary surface between two layers. The entire bump fully melts in the reaction so that the semiconductor chip may be securely connected on the substrate.

摘要翻译： 半导体芯片设置有通过交替地构建能够形成共晶合金的两种类型的金属材料形成的凸块，因此在两层之间的每个边界面处发生共晶合金反应。 反应中的整个凸起完全熔化，使得半导体芯片可以牢固地连接在基板上。

公开(公告)号：US5414303A

公开(公告)日：1995-05-09

申请号：US205670

申请日：1994-03-02

申请人： Stephen G. Gonya ,  James K. Lake ,  Randy C. Long ,  Roger N. Wild

发明人： Stephen G. Gonya ,  James K. Lake ,  Randy C. Long ,  Roger N. Wild

IPC分类号： B23K35/26 ,  C22C13/00 ,  H05K3/34 ,  H01L23/48 ,  H01L29/46 ,  H01L29/64

CPC分类号： B23K35/262 ,  C22C13/00 ,  H01L2924/0002

摘要： Disclosed is a high solidus temperature, high service temperature, high strength ternary solder alloy. The components of the alloy are a major portion of Sn and lesser portions of Bi, and In.

摘要翻译： 公开了高固相线温度，高使用温度，高强度三元焊料合金。 合金的组分是Sn的主要部分，Bi和In的较少部分。

公开(公告)号：US5414272A

公开(公告)日：1995-05-09

申请号：US224192

申请日：1994-04-07

申请人： Nobuo Watanabe ,  Masahiko Okunuki ,  Takeo Tsukamoto

发明人： Nobuo Watanabe ,  Masahiko Okunuki ,  Takeo Tsukamoto

IPC分类号： H01L29/872 ,  H01J1/308 ,  H01J9/02 ,  H01L29/47 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC分类号： H01J1/308 ,  H01J9/022

摘要： A semiconductor element emission element having a Schottky junction in a surface region of a semiconductor, comprises a first region having a first carrier concentration, a second region having a second carrier concentration, and a third region having a third carrier concentration. All of the regions are located below an electrode forming the Schottky junction. The first, second, and third carrier concentrations satisfy a condition that the first carrier concentration of the first region is higher than the second carrier concentration of the second region and that the second carrier concentration of the second region is higher than the third carrier concentration of the third region. The first, second, and third regions have a structure that at least one second region having the second carrier concentration is located inside the third region of the third carrier concentration, and that at lease one first region having the first carrier concentration is located inside said second region having the second carrier concentration.

摘要翻译： 在半导体的表面区域中具有肖特基结的半导体元件发光元件包括具有第一载流子浓度的第一区域，具有第二载流子浓度的第二区域和具有第三载流子浓度的第三区域。 所有区域都位于形成肖特基结的电极之下。 第一，第二和第三载流子浓度满足第一区域的第一载流子浓度高于第二区域的第二载流子浓度，并且第二区域的第二载流子浓度高于第二区域的第三载流子浓度的条件 第三个地区。 第一，第二和第三区域具有以下结构：具有第二载流子浓度的至少一个第二区域位于第三载流子浓度的第三区域内，并且至少具有第一载流子浓度的第一区域位于所述 第二区域具有第二载流子浓度。

公开(公告)号：US5285109A

公开(公告)日：1994-02-08

申请号：US705594

申请日：1991-05-24

申请人： Tadashi Tomikawa ,  Tunenobu Kimoto ,  Nobuhiko Fujita

发明人： Tadashi Tomikawa ,  Tunenobu Kimoto ,  Nobuhiko Fujita

IPC分类号： H01L29/20 ,  H01L29/45 ,  H01L29/48 ,  H01L29/46 ,  H01L29/62 ,  H01L29/64

CPC分类号： H01L29/20 ,  H01L29/452 ,  Y10S438/932

摘要： An ohmic contact electrode formed on an n-type semiconductor cubic boron nitride by using a IVa metal; an alloy with a IVa metal; a metal with Si or S; an alloy with Si or S; a metal with B, Al, Ga, or In; an alloy with B, Al, Ga, or In; a Va metal; or an alloy with a Va metal.

摘要翻译： 通过使用IVa金属在n型半导体立方氮化硼上形成的欧姆接触电极; 具有IVa金属的合金; 具有Si或S的金属; 与Si或S的合金; 具有B，Al，Ga或In的金属; 具有B，Al，Ga或In的合金; Va金属 或与Va金属的合金。

公开(公告)号：US5250848A

公开(公告)日：1993-10-05

申请号：US737473

申请日：1991-07-30

申请人： Frederick R. Christie ,  Kostas I. Papathomas ,  David W. Wang

发明人： Frederick R. Christie ,  Kostas I. Papathomas ,  David W. Wang

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/29 ,  H05K3/28 ,  H05K3/34 ,  H01L23/48 ,  H01L29/40 ,  H01L29/64 ,  H01L39/02

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/293 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/83856 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/284 ,  H05K3/285 ,  H05K3/3431 ,  Y10T428/31504 ,  Y10T428/31547

摘要： Solder interconnection whereby the gap created by solder connections between a carrier substrate and semiconductor device is filled with a composition obtained from curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof; filler having a maximum particle size of 31 microns and being at least substantially free of alpha particle emissions.

摘要翻译： 焊接互连，由此通过固化含有脂环族聚环氧化物和/或可固化的氰酸酯或其预聚物的制剂获得的组合物填充由载体基底和半导体器件之间的焊料连接所产生的间隙; 填料的最大粒度为31微米，至少基本上不含α粒子的排放。

公开(公告)号：US4139857A

公开(公告)日：1979-02-13

申请号：US705696

申请日：1976-07-15

申请人： Toshinori Takagi ,  Kiyoshi Morimoto ,  Yukihiko Utamura

发明人： Toshinori Takagi ,  Kiyoshi Morimoto ,  Yukihiko Utamura

IPC分类号： H01L21/203 ,  H01L29/04 ,  H01L31/07 ,  H01L31/18 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC分类号： H01L21/0242 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02631 ,  H01L29/04 ,  H01L31/07 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A Schottky barrier type solid-state element and a method of producing the same, the Schottky barrier type solid-state element comprising a Schottky barrier type element portion consisting of a metallic board and a semiconductor film layer provided on the metallic board, the metallic board being formed of such a metal as can form a Schottky barrier between itself and the semiconductor film layer, and a semiconductor-side terminal electrode provided on the external surface of the semiconductor film layer so as to obtain an ohmic contact therewith, wherein at least the semiconductor film layer is formed by what is called the ionized-cluster-beam deposition process.

摘要翻译： 一种肖特基势垒型固体元素及其制造方法，肖特基势垒型固体元素包括由金属板和设置在金属板上的半导体膜层构成的肖特基势垒型元件部，金属板 由能够在其与半导体膜层之间形成肖特基势垒的金属形成，并且设置在半导体膜层的外表面上以便与其形成欧姆接触的半导体侧端子电极，其中至少 半导体膜层由所谓的离子束聚束束沉积工艺形成。

公开(公告)号：US4038676A

公开(公告)日：1977-07-26

申请号：US634038

申请日：1975-11-21

申请人： Karl Goser

发明人： Karl Goser

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L23/535 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/735 ,  H01L29/72 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC分类号： H01L27/0688 ,  H01L21/8222 ,  H01L23/535 ,  H01L29/735 ,  H01L2924/0002

摘要： A pair of bipolar transistors are formed in a semiconductor substrate with each transistor having at least one emitter, one base and at least one collector. At least the base is in the form of a doped zone in the substrate. The two base zones are electrically conductively connected to one another and the transistors are constructed or arranged in the substrate in such a manner that in each case free boundary faces of the two base zones lie opposite one another. The base connection is formed by an additionally doped zone in the interspace between the base zones, the doped zone having the same type of doping as the base zones.

公开(公告)号：US4005469A

公开(公告)日：1977-01-25

申请号：US588918

申请日：1975-06-20

申请人： Augustine Wei-Chun Chang ,  Vincent Joseph Lucarini

发明人： Augustine Wei-Chun Chang ,  Vincent Joseph Lucarini

IPC分类号： H01L27/06 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/07 ,  H01L29/10 ,  H01L29/47 ,  H01L29/73 ,  H01L29/872 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64 ,  H01L29/72

CPC分类号： H01L27/0766 ,  H01L21/743 ,  H01L29/1004

摘要： A clamped epi-base NPN transistor with very short saturation time constant is obtained by ion implantation in the P-type base region to convert a portion thereof to N.sup.- conductivity type contiguous to the collector reach-through region. The converted region is contacted by an extended metal electrode which also contacts the base region. The metal electrode establishes ohmic contact to the base region and Schottky diode contact to the converted region and to the collector region connected thereto.

摘要翻译： 通过在P型基极区域中离子注入来获得具有非常短的饱和时间常数的被钳位的epi-base NPN晶体管，以将它们的一部分转换为与集电极通过区域相邻的N +导电类型。 转换的区域与也接触基极区域的延伸金属电极接触。 金属电极与基极区域形成欧姆接触，肖特基二极管与转换区域和与其连接的集电极区域接触。

公开(公告)号：US3964084A

公开(公告)日：1976-06-15

申请号：US478506

申请日：1974-06-12

申请人： John Marshall Andrews, Jr. ,  Robert Morgan Ryder ,  Simon Min Sze

发明人： John Marshall Andrews, Jr. ,  Robert Morgan Ryder ,  Simon Min Sze

IPC分类号： H01L21/00 ,  H01L29/00 ,  H01L29/872 ,  H01L29/48 ,  H01L29/56 ,  H01L29/64

CPC分类号： H01L29/872 ,  H01L21/00 ,  H01L29/00

摘要： A Schottky barrier contact includes a thin layer of high carrier concentration impurities ion implanted over the contact surface of the semiconductor. This reduces the electronic barrier height, increases the tunneling component, and thus reduces the forward-bias turn-on voltage of the diode. The implanted layer has a carrier concentration at least ten times that of the semiconductor substrate, and a thickness smaller than the width of the inherent depletion region resulting from the internally generated electric field at the metal-semiconductor interface. An implanted layer of the opposite conductivity type raises the barrier height.