公开(公告)号：US4926260A

公开(公告)日：1990-05-15

申请号：US345394

申请日：1989-05-01

申请人： Peter H. Frencken ,  Antonius H. H. J. Nillesen ,  Simon J. Brand

发明人： Peter H. Frencken ,  Antonius H. H. J. Nillesen ,  Simon J. Brand

IPC分类号： H04N5/04 ,  G11B20/10 ,  H04N5/05 ,  H04N7/01

CPC分类号： H04N5/05

摘要： In order that one clock signal generator in a digital video signal processing circuit comprising a line-coupled clock signal generator and using, for example one or more field memories is sufficient for writing and reading these memories and can still process a signal from a video recorder, the control loop of the clock signal generator uses a comb filter circuit which rapidly corrects regular variations in an output signal of a phase detector of the control loop, which variations are caused by the head drum of the video recorder, without having to adapt the proportioning of a conventional loop filter circuit.