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1.发明授权Digital chrominance processor with a phase and frequency controlled digital oscillator independent of the stable oscillator frequency 失效数字色度处理器具有独立于稳定振荡器频率的相位和频率控制的数字振荡器
公开(公告)号：US4682209A
公开(公告)日：1987-07-21
申请号：US836236
申请日：1986-03-04
摘要： In a digital chrominance signal processing circuit for a chrominance signal which is sampled at a frequency equal to a number of times the chrominance subcarrier frequency, this frequency can be made variable, without switching to a different crystal frequency, by using a clock signal produced by a crystal oscillator (65) and a digital oscillator (71) which is controlled via a digital number (at 73) and whose quiescent frequency can be changed by changing a number to be applied to an input (95) of an adder circuit (85). Additionally, the adder circuit (85) is supplied with a number representing a control signal (at 88) and applies via its output (83) the frequency-determining digital number to an input (73) of the digital oscillator (71).
摘要翻译： 在色度信号的数字色度信号处理电路中，该色度信号以等于色度副载波频率的次数进行采样，可以使频率变化而不切换到不同的晶体频率，通过使用由 通过数字（数字73）控制的晶体振荡器（65）和数字振荡器（71），其静态频率可以通过改变要加到加法器电路（85）的输入端（95）的数量来改变 ）。 此外，加法器电路（85）被提供有表示控制信号的数字（在88处），并经由其输出（83）将频率确定数字数字施加到数字振荡器（71）的输入端（73）。
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2.发明授权
公开(公告)号：US4513388A
公开(公告)日：1985-04-23
申请号：US601093
申请日：1984-04-16
申请人： Hendrikus J. M. Veendrick , Leonardus C. M. G. Pfennings , Johannes G. Raven , Antonius H. H. J. Nillesen
发明人： Hendrikus J. M. Veendrick , Leonardus C. M. G. Pfennings , Johannes G. Raven , Antonius H. H. J. Nillesen
IPC分类号： G06F7/52 , G06F7/50 , G06F7/508 , G06F7/523 , G06F7/53 , G06F7/544 , G06F17/10 , H03H17/02 , H03H17/04 , H03K17/00 , G06F7/38
CPC分类号： G06F7/5443
摘要： A device is described for electronically executing a mathematical operation, being Z=KA+(1-K)B. It is also described how this device or how several of such devices can be used for the design of a number of realizations, such as a recursive filter, a digital mixer etc. The basic idea is the electronic implementation of a mathematical function for binary variables.
摘要翻译： 描述了用于电子地执行数学运算的装置，即Z = KA +（1-K）B。 还描述了该设备或者这些设备中的几个可以用于多个实现的设计，例如递归滤波器，数字混频器等。基本思想是用于二进制变量的数学函数的电子实现 。
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公开(公告)号：US4809207A
公开(公告)日：1989-02-28
申请号：US829574
申请日：1986-02-14
CPC分类号： H03H17/0461
摘要： Continued circulation of residual signal values in a recursive first order digital video signal filter, in which a truncation circuit (37) is used for eliminating a portion of the least significant bits in the feedback signal path (31, 37, 43, 11) of the filter, is prevented by adding (19, 47, 51) before the trucation circuit a logic one value to the feedback signal path at the level of the least significant bit of the bits remaining after the truncation circuit. Video signal filters of such a type are frequently used as noise suppression circuits.
摘要翻译： 在递归一阶数字视频信号滤波器中继续循环残留信号值，其中截断电路（37）用于消除反馈信号路径（31,37,43,11）中的一部分最低有效位， 通过在截断电路之前的剩余的比特的最低有效位的电平上向反馈信号路径添加逻辑1值（19,47,51）来防止滤波器。 这种类型的视频信号滤波器经常用作噪声抑制电路。
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4.发明授权Demodulation circuit for a digitized chrominance signal having a sampling signal oscillator coupled to a chrominance signal oscillator 失效用于具有耦合到色度信号振荡器的采样信号振荡器的数字化色度信号的解调电路
公开(公告)号：US4625232A
公开(公告)日：1986-11-25
申请号：US560768
申请日：1983-12-12
CPC分类号： H04N11/165
摘要： In a digital demodulation circuit for a chrominance signal of a color television signal having a first digital oscillator (35) for producing reference signals and a phase control loop (29, 17, 19, 49, 43) therefor, there is added in the phase control loop a signal combination (at 56) which is obtained from a phase control loop (67, 63, 59) of a second digital oscillator (77). This second digital oscillator derives the sampling frequency for sampling the chrominance signal from a signal source (83) of a constant frequency and couples this sampling frequency to the horizontal deflection frequency. By the addition in the phase control loop of the first oscillator, variations in the horizontal deflection frequency cannot lead to the undesired phenomenon of the first digital oscillator being pulled to a side-band frequency of the color subcarrier wave.
摘要翻译： 在具有用于产生参考信号的第一数字振荡器（35）和用于产生参考信号的相位控制回路（29,17,19,49,43）的彩色电视信号的色度信号的数字解调电路中，在该相位 控制环路是从第二数字振荡器（77）的相位控制回路（67,63,59）获得的信号组合（在56处）。 该第二数字振荡器导出采样频率以从恒定频率的信号源（83）采样色度信号，并将该采样频率耦合到水平偏转频率。 通过在第一振荡器的相位控制环路中相加，水平偏转频率的变化不会导致第一数字振荡器被拉到彩色副载波的边带频率的不期望的现象。
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公开(公告)号：US4926260A
公开(公告)日：1990-05-15
申请号：US345394
申请日：1989-05-01
CPC分类号： H04N5/05
摘要： In order that one clock signal generator in a digital video signal processing circuit comprising a line-coupled clock signal generator and using, for example one or more field memories is sufficient for writing and reading these memories and can still process a signal from a video recorder, the control loop of the clock signal generator uses a comb filter circuit which rapidly corrects regular variations in an output signal of a phase detector of the control loop, which variations are caused by the head drum of the video recorder, without having to adapt the proportioning of a conventional loop filter circuit.
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公开(公告)号：US06297849B1
公开(公告)日：2001-10-02
申请号：US09213532
申请日：1998-12-17
IPC分类号： H04N504
CPC分类号： H03L7/0994 , H04N5/126
摘要： An output timebase corrector converts orthogonal sampled video (VS) into asynchronous sampled video (VOS) with asynchronous sample values occurring at clock instants (TC) of a clock signal (CLK). The asynchronous sampled video (VOS) is displayed on a display screen of a display device (DD). A discrete time oscillator (DTO) of a time-discrete phase-locked loop (PLL) supplies a time base signal (OS). The time-discrete phase-locked loop (PLL) determines a phase difference (PE) between the time base signal (OS) and reference instants (FB) indicating a timing of a line deflection of the display device (DD) to obtain the time base signal (OS) being locked to the reference instants (FB). The time base signal (OS) controls a sample rate converter (SRC) such that the asynchronous video values (VOS) which occur at the clock instants (TC) are interpolated from the orthogonal sampled video (VS) by the sample rate converter (SRC) such that the video signal is displayed on the correct position on the display screen. In the output timebase corrector according to the invention all circuits are clocked by clock signals (CLK) originating from one and the same clock generator (OSC).
摘要翻译： 输出时基校正器将正交采样视频（VS）转换成异步采样视频（VOS），其中异步采样值出现在时钟信号（CLK）的时钟时刻（TC）。 异步采样视频（VOS）显示在显示设备（DD）的显示屏幕上。 时分离锁相环（PLL）的离散时间振荡器（DTO）提供时基信号（OS）。 时间离散锁相环（PLL）确定时基信号（OS）和指示显示设备（DD）的线路偏转的定时的参考时刻（FB）之间的相位差（PE），以获得时间 基本信号（OS）被锁定到参考时刻（FB）。 时基信号（OS）控制采样率转换器（SRC），使得在时钟时刻（TC）发生的异步视频值（VOS）由采样率转换器（SRC）从正交采样视频（VS）内插 ），使得视频信号显示在显示屏上的正确位置。 在根据本发明的输出时基校正器中，所有电路由源自同一个时钟发生器（OSC）的时钟信号（CLK）计时。
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公开(公告)号：US4574307A
公开(公告)日：1986-03-04
申请号：US529893
申请日：1983-09-07
摘要： A line synchronizing circuit for a picture display device comprising a control loop for controlling a line oscillator. An incoming line synchronizing signal and also a reference signal generated by the oscillator are applied to a phase discriminator circuit. The output signal of the phase discriminator circuit is smoothed to obtain the control voltage for the oscillator. Pull-in of the control loop is established by means of a coincidence detector. Prior to that, an edge of the reference signal is compared with the center instant of a line synchronizing pulse. When the control loop is in the pulled-in state, it is changed by the coincidence detector to compare the leading edge of a line synchronizing pulse to the center instant between the said edge of the reference signal and its first preceding edge.
摘要翻译： 一种用于图像显示装置的行同步电路，包括用于控制线路振荡器的控制环路。 输入行同步信号以及由振荡器产生的参考信号被施加到鉴相器电路。 相位鉴别电路的输出信号被平滑以获得振荡器的控制电压。 通过重合检测器建立控制回路的拉入。 在此之前，将参考信号的边沿与行同步脉冲的中心时刻进行比较。 当控制回路处于拉入状态时，它由重合检测器改变，以将线同步脉冲的前沿与参考信号的所述边缘与其第一先前边缘之间的中心时刻进行比较。
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公开(公告)号：US5625581A
公开(公告)日：1997-04-29
申请号：US340570
申请日：1994-11-16
CPC分类号： H03H17/0027
摘要： A time-discrete signal is delayed by a selectable fraction (.delta.) of a sampling period of the time-discrete signal. First (F1) and second (F2) differential signals having mutually different phase characteristics are derived from the time-discrete signal and are subsequently combined (MIX) dependent upon the selectable fraction (.delta.) to obtain a phase-adjusted correction signal. The product of the selectable fraction (.delta.) and the correction signal is added to the time-discrete signal to obtain a time-discrete signal which has been delayed by the selectable fraction (.delta.). The second differential signal is obtained by means of a differentiator with asymmetric coefficients in order to optimise the transfer characteristic for .delta.=0.5.
摘要翻译： 时间离散信号被延迟时间离散信号的采样周期的可选择分数（delta）。 从时间离散信号导出具有相互不同的相位特性的第一（F1）和第二（F2）差分信号，并且随后根据可选择分数（delta）组合（MIX）以获得相位调整的校正信号。 将可选择分数（delta）和校正信号的乘积加到时间离散信号中，以获得延迟了可选择分数（delta）的时间离散信号。 通过具有不对称系数的微分器获得第二差分信号，以优化Δ= 0.5的传递特性。
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公开(公告)号：US5349548A
公开(公告)日：1994-09-20
申请号：US61358
申请日：1993-05-13
CPC分类号： H03H17/0027
摘要： A non-integral delay circuit for delaying a digital signal by a selectable fraction (.delta.) of a sampling period of the digital signal includes a first differentiator (S3) to obtain a first differential signal (F1) having a first phase characteristic with respect to the digital signal, a second differentiator (D) to obtain a second differential signal (F2) having a second phase characteristic with respect to the digital signal, the first and second phase characteristics differing from each other, a mixer (MIX) for combining the first (F1) and second (F2) differential signals in dependence on the selectable fraction (.delta.) to obtain a phase-adjusted correction signal, and an adder (A9) which adds a product (M3) of the selectable fraction (.delta.) and the phase-adjusted correction signal to the digital signal, to obtain the digital signal delayed by the selectable fraction (.delta.) of the sampling period of the digital signal.
摘要翻译： 用于将数字信号延迟数字信号的采样周期的可选择分数（delta）的非积分延迟电路包括第一微分器（S3），以获得第一差分信号（F1），其具有相对于 数字信号，第二微分器（D），以获得相对于数字信号具有第二相位特性的第二差分信号（F2），第一和第二相位特性彼此不同;混频器（MIX），用于将 第一（F1）和第二（F2）差分信号，以获得相位调整的校正信号;以及加法器（A9），其将可选择分数（delta）的乘积（M3）和 对数字信号进行相位调整的校正信号，以获得由数字信号的采样周期的可选择分数（delta）延迟的数字信号。
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公开(公告)号：US4947380A
公开(公告)日：1990-08-07
申请号：US208186
申请日：1988-06-16
申请人： Adrianus T. Van Zanten , Hendrikus J. M. Veendrick , Frits A. Steenhof , Peter H. Frencken , Antonius H. H. J. Nillesen , Cornelis G. L. M. Van Der Sanden
发明人： Adrianus T. Van Zanten , Hendrikus J. M. Veendrick , Frits A. Steenhof , Peter H. Frencken , Antonius H. H. J. Nillesen , Cornelis G. L. M. Van Der Sanden
CPC分类号： G11C19/287 , G11C27/04
摘要： The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.
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