公开(公告)号：US06170053A

公开(公告)日：2001-01-02

申请号：US08883998

申请日：1997-06-27

Applicant: Timothy D. Anderson ,  Simonjit Dutta ,  Jonathan H. Shiell

Inventor： Timothy D. Anderson ,  Simonjit Dutta ,  Jonathan H. Shiell

IPC: G06F932

CPC classification number: G06F9/3806 ,  G06F9/3844

Abstract: A microprocessor with an execution stage (26) including a plurality of execution units and an instruction memory (32) for storing instructions. The microprocessor further includes circuitry for retrieving (14) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (30) for storing a plurality of information fields (30r) corresponding to a branch instruction. The information fields include at least a target instruction address (Tn), a prediction field (Pn) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPAn) indicating accuracy for past prediction fields. In operation, the circuitry for retrieving instructions retrieves (46), as a next instruction to follow the branch instruction, an instruction corresponding to the target instruction address in response to a function (TPn) responsive to the accuracy measure exceeding a predetermined threshold and the prediction field indicating program flow should pass to the target instruction address. Additionally, the circuitry for retrieving instructions retrieves (54), in response to the function responsive to the accuracy measure not exceeding a predetermined threshold, a first group of instructions, wherein the first group of instructions is sequentially arranged after the branching branch instruction and includes an instruction corresponding to the target instruction address.

Abstract translation: 具有包括多个执行单元的执行级（26）的微处理器和用于存储指令的指令存储器（32）。 微处理器还包括用于从指令存储器检索（14）指令的电路。 该检索电路可以通过多个执行单元之一执行另一个指令同时检索一个指令。 此外，该检索电路包括用于存储对应于分支指令的多个信息字段（30r）的分支目标存储器（30）。 信息字段至少包括目标指令地址（Tn），指示程序流程是否应该传递到目标指令地址的预测字段（Pn）以及指示过去预测字段的精度的精度测量（PPAn）。 在操作中，用于检索指令的电路响应于超过预定阈值的精度测量值而响应于功能（TPn），检索（46）作为跟随分支指令的下一指令，对应于目标指令地址的指令， 指示程序流的预测字段应传递到目标指令地址。 另外，用于检索指令的电路响应于响应于不超过预定阈值的精度测量的函数而检索（54）第一组指令，其中第一组指令被顺序地布置在分支分支指令之后并且包括 与目标指令地址对应的指令。

公开(公告)号：US20210141723A1

公开(公告)日：2021-05-13

申请号：US17156593

申请日：2021-01-24

Applicant: Han B. Lee ,  Simonjit Dutta ,  Rodolfo G. Esteves Jaramillo ,  Poornima S. Kumar ,  Chanchala Roy Lairikyengbam ,  Weilin Wang

Inventor： Han B. Lee ,  Simonjit Dutta ,  Rodolfo G. Esteves Jaramillo ,  Poornima S. Kumar ,  Chanchala Roy Lairikyengbam ,  Weilin Wang

IPC: G06F12/02 ,  G06F9/54

Abstract: Live objects in heap memory exceeding a threshold size and that have not been recently accessed are compressed or offloaded to secondary memory or storage. Compressing or offloading an object can further be based on how old the object is, which can be determined based on how many garbage collections the object has survived. Objects comprising references to other objects can be split into two sub-objects, one containing value fields that is compressed or offloaded and one containing reference fields that remains uncompressed in heap memory. Heap memory can undergo compaction after objects are compressed or offloaded. Compression accelerators can be used for compression and the decision of whether to compress or offload an object can be based on accelerator throughput, latency, availability, as well as other computing system metrics or characteristics. The compressing and offloading of objects and subsequent compaction can make more heap memory available for object allocation.

公开(公告)号：US5881277A

公开(公告)日：1999-03-09

申请号：US874786

申请日：1997-06-13

Applicant: James O. Bondi ,  Simonjit Dutta ,  Ashwini K. Nanda

Inventor： James O. Bondi ,  Simonjit Dutta ,  Ashwini K. Nanda

IPC: G06F9/38

CPC classification number: G06F9/382 ,  G06F9/3804 ,  G06F9/3842

Abstract: A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit. The output of the multiplexer is coupled to an input of a second stage (50) of the intermediary stages, wherein the second stage follows the first stage. Other circuits, systems, and methods are also disclosed and claimed.

Abstract translation: 一种微处理器，包括包括多个连续指令级的指令流水线（36）。 指令通过多个中间级（40至52）和多个连续指令级的结束级（54）从初始阶段（38）传递。 微处理器还包括一个存储电路（58），它被耦合以接收从中间级的第一级（48）输出的程序线程信息。 此外，微处理器包括选择电路（56），其包括第一输入端，第二输入端和用于从其第一和第二输入端输出输出信号的输出端。 选择电路的第一输入被耦合以接收从第一级输出的输出信息。 选择电路的第二输入被耦合以接收从存储电路输出的程序线程信息。 多路复用器的输出耦合到中间级的第二级（50）的输入端，其中第二级跟随第一级。 还公开并要求保护其他电路，系统和方法。