摘要:
In order to enable a pointer register device including registers called shadow registers to conduct updating operation rapidly by arithmetic operation of a pointer value between the registers, a front/back register set includes a first register and a second register. A switch control section allows a read select switch and a write select switch to select different registers. When the read select switch selects the first register and the write select switch selects the second register, the sum obtained by an adder can be stored in the second register while retaining the pointer value of the first register. In this case, the pointer value need not be transferred between the registers.
摘要:
A method for providing single step log-on access for a subscriber to a computer network. The computer network is differentiated into public and private areas. Secure access to the private areas is provided by a Service Selection Gateway (SSG) Server, introduced between a conventional Network Access Server (NAS) and an Authentication Authorization and Accounting (AAA) Server. The SSG Server intercepts and manipulates packets of data exchanged between the NAS and the AAA Server to obtain all the information it needs to automatically log the user on when the user logs on to the NAS. An authorized user is thus spared the task of having to re-enter username and password data or launch a separate application in order to gain secure access to private areas of the network.
摘要:
There is provided a decoupled fetch-execute engine with static branch prediction support. A method for prefetching targets of branch instructions in a computer processing system having instruction fetch decoupled from an execution pipeline includes the step of generating a prepare-to-branch (PBR) operation. The PBR operation includes address bits corresponding to a branch paired thereto and address bits corresponding to an expected target of the branch. The execution of the PBR operation is scheduled prior to execution of the paired branch to enforce a desired latency therebetween. Upon execution of the PBR operation, it is determined whether the paired branch is available using the address bits of the PBR operation corresponding to the paired branch. When the paired branch is available, the expected branch target is fetched using the address bits of the PBR operation corresponding to the expected branch target.
摘要:
The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding location to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execution of a current instruction.
摘要:
A method for providing single step log-on access for a subscriber to a computer network. The computer network is differentiated into public and private areas. Secure access to the private areas is provided by a Service Selection Gateway (SSG) Server, introduced between a conventional Network Access Server (NAS) and an Authentication Authorization and Accounting (AAA) Server. The SSG Server intercepts and manipulates packets of data exchanged between the NAS and the AAA Server to obtain all the information it needs to automatically log the user on when the user logs on to the NAS. An authorized user is thus spared the task of having to re-enter username and password data or launch a separate application in order to gain secure access to private areas of the network.
摘要:
An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.
摘要:
In an instruction a relative jump distance is expressed as a number of instructions rather than as a number of addresses. Instructions have various lengths. After encountering the instruction the processing device loads the following instructions but suppresses execution of a set of instructions that consists of the number of instructions expressed in the relative jump instruction.
摘要:
An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus has a static branch predictor, a mandatory signal, and a biased prediction correlator. The static branch predictor provides a predicted outcome for a branch instruction, and determines if the branch instruction is a biased outcome conditional branch instruction. The mandatory signal is coupled to the static branch predictor and indicates whether or not the branch instruction is the biased outcome conditional branch instruction, thereby indicating whether or not the predicted outcome takes precedence over a dynamic branch prediction for the branch instruction. The biased prediction correlator is coupled to the static branch predictor and the mandatory signal. The biased prediction correlator receives the predicted outcome, the mandatory signal, and the dynamic branch prediction. The biased prediction correlator favors the dynamic branch prediction over the predicted outcome. If the mandatory signal indicates that the branch instruction is a biased outcome conditional branch instruction, however, then the biased prediction correlator favors the predicted outcome over the dynamic branch prediction.
摘要:
A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.
摘要:
Reliable branch predictions for real-time applications reduce both conditional branch execution time and uncertainties associated with their prediction in a computer implemented application. One method ensures that certain conditional branches are always correctly predicted, effectively converting them to jump instructions during program execution. Another method exploits the fact that some conditional branches always branch in the same direction within a task invocation, although that direction may vary across invocations. These methods improve computer processor utilization and performance.