公开(公告)号：US07003746B2

公开(公告)日：2006-02-21

申请号：US10686022

申请日：2003-10-14

申请人： Stanley M. Hyduke ,  Slawomir Grabowski

发明人： Stanley M. Hyduke ,  Slawomir Grabowski

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F7/62 ,  G06F9/455

CPC分类号： G06F17/5027

摘要： A method and system for accelerating software simulator operation with the aid of reprogrammable hardware such as Field Programmable Gate Array devices (FPGA). The method and system aid in emulation and prototyping of Application Specific Integrated Circuits (ASIC) digital circuit designs by means of reprogrammable devices. The system includes a design verification manager and software program that includes subroutines of finding clock sources, finding synchronous primitives that are receiving clock signals from the clock sources, and a subroutine for inserting edge detector circuits between such clock sources and synchronous primitives. This new method allows eliminating of clock timing issues by applying basic design clocks to the clock enable instead of clock trigger inputs and generating and applying to clock trigger inputs a new clock that is automatically delayed in respect to all other clocks in the design. This system solves the major obstacle for automatic retargeting of ASIC designs into reprogrammable devices that have different timings of the clocking chains in ASICs and FPGAs that result in triggering of associated flip-flops and latches at different times.

摘要翻译： 借助于现场可编程门阵列器件（FPGA）等可编程硬件来加速软件仿真器运行的方法和系统。 该方法和系统通过可重复编程的设备来辅助应用专用集成电路（ASIC）数字电路设计的仿真和原型设计。 该系统包括设计验证管理器和软件程序，其包括查找时钟源的子程序，发现从时钟源接收时钟信号的同步原语，以及用于在这样的时钟源和同步原语之间插入边缘检测器电路的子程序。 这种新方法允许通过将基本设计时钟应用于时钟使能而不是时钟触发输入来消除时钟定时问题，并产生并向时钟触发输入应用相对于设计中所有其他时钟自动延迟的新时钟。 该系统解决了将ASIC设计自动重新定位到可编程器件中的主要障碍，这些器件具有ASIC和FPGA中时钟链的不同时序，导致在不同时间触发相关的触发器和锁存器。

公开(公告)号：US06578133B1

公开(公告)日：2003-06-10

申请号：US09512091

申请日：2000-02-24

申请人： Stanley M. Hyduke

发明人： Stanley M. Hyduke

IPC分类号： G06F1516

CPC分类号： G06F17/5022 ,  G06F15/8007 ,  G06F17/5045

摘要： A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description language (HDL) based designs into a set of logic equations and single bit arithmetic-logic operations executed by a set of parallel operating sequencers. The system includes software for converting netlists and HDL designs into Boolean logic equations, and a compiler for distributing these logic equations between multiple sequencers. Each sequencer is comprised of a logic processor and the associated program memory for storing the executable code of the assigned Boolean logic equations and data memory for storing the results of processing of logic equations. To synchronize execution of logic equations by multiple sequencers, all program memories are addressed by one common address register. The processing of logic equations is arranged in such a manner that their outputs can be read by synchronized read instructions in the interconnected sequencers, eliminating any need for control signals.

摘要翻译： 一种使用一组同步定序器来设计和实现数字集成电路的系统，允许系统级设计的快速和有效的并行处理。 该系统和方法将基于数字原理图和硬件描述语言（HDL）的设计转换为由一组并行操作定序器执行的一组逻辑方程和单位运算逻辑运算。 该系统包括用于将网表和HDL设计转换为布尔逻辑方程的软件，以及用于在多个定序器之间分配这些逻辑方程式的编译器。 每个定序器由逻辑处理器和用于存储分配的布尔逻辑方程的可执行代码的相关程序存储器和用于存储逻辑方程的处理结果的数据存储器组成。 为了通过多个定序器同步逻辑方程的执行，所有程序存储器都由一个公共地址寄存器寻址。 逻辑方程式的处理方式使得它们的输出可以通过互连的顺控程序中的同步读取指令读取，从而消除对控制信号的任何需要。

公开(公告)号：US06915410B2

公开(公告)日：2005-07-05

申请号：US10350480

申请日：2003-01-23

申请人： Stanley M. Hyduke

发明人： Stanley M. Hyduke

IPC分类号： G06F15/80 ,  G06F17/50 ,  G06F15/173

CPC分类号： G06F17/5022 ,  G06F15/8007 ,  G06F17/5045

摘要： A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description language (HDL) based designs into a set of logic equations and single bit arithmetic-logic operations executed by a set of parallel operating sequencers. The system includes software for converting netlists and HDL designs into Boolean logic equations, and a compiler for distributing these logic equations between multiple sequencers. Each sequencer is comprised of a logic processor and the associated program memory for storing the executable code of the assigned Boolean logic equations and data memory for storing the results of processing of logic equations. To synchronize execution of logic equations by multiple sequencers, all program memories are addressed by one common address register. The processing of logic equations is arranged in such a manner that their outputs can be read by synchronized read instructions in the interconnected sequencers, eliminating any need for control signals.

摘要翻译： 一种使用一组同步定序器来设计和实现数字集成电路的系统，允许系统级设计的快速和有效的并行处理。 该系统和方法将基于数字原理图和硬件描述语言（HDL）的设计转换为由一组并行操作定序器执行的一组逻辑方程和单位运算逻辑运算。 该系统包括用于将网表和HDL设计转换为布尔逻辑方程的软件，以及用于在多个定序器之间分配这些逻辑方程式的编译器。 每个定序器由逻辑处理器和用于存储分配的布尔逻辑方程的可执行代码的相关程序存储器和用于存储逻辑方程的处理结果的数据存储器组成。 为了通过多个定序器同步逻辑方程的执行，所有程序存储器都由一个公共地址寄存器寻址。 逻辑方程式的处理方式使得它们的输出可以通过互连的顺控程序中的同步读取指令读取，从而消除对控制信号的任何需要。

公开(公告)号：US4827427A

公开(公告)日：1989-05-02

申请号：US21925

申请日：1987-03-05

申请人： Stanley M. Hyduke

发明人： Stanley M. Hyduke

IPC分类号： G06F17/50 ,  G06F15/20

CPC分类号： G06F17/5022

摘要： A computer aided logic design system for instantaneously compiling circuit component entries into a schematic model which provides immediate simulation of each entry or deletion into the electronic circuit schematic. The system includes software for processing logic designs which produces a signal table for storing all inputs and outputs of chips stored in a specification table. The processor also produces a call table that lists all chips from the chips specification table from which chip models can be retreived and executed. Additionally, a software routine produces a netlist transfer table that specifies the transfer of signals within the signal table produced by software processing, which correspond to the signal distribution in the circuit being designed. After production of the signal table, specification table, call table and netlist transfer table, a software processing routine executes sequential values retrieved from the call table and netlist transfer table to create a second signal table which is compared with the first signal table. The software processing routine continuous to execute values retrieved from the call table and netlist transfer table and compare the first and second signal tables until both the second signal table being created is identical with the first signal table stored in memory. The software processing means also includes a delay which delays sequential processing until the comparing step for comparing the second signal table with the first signal table reaches a stable state.

摘要翻译： 一种计算机辅助逻辑设计系统，用于将电路组件条目瞬时编译成示意图模型，其提供对每个条目或删除到电子电路原理图的即时仿真。 该系统包括用于处理逻辑设计的软件，其产生用于存储规范表中存储的芯片的所有输入和输出的信号表。 处理器还产生一个调用表，其中列出了芯片规格表中的所有芯片，从哪个芯片模型可以被检索和执行。 此外，软件程序产生一个网表转移表，其指定由软件处理产生的信号表中的信号的传输，其与所设计的电路中的信号分布相对应。 在产生信号表，规范表，呼叫表和网表转移表之后，软件处理例程执行从呼叫表和网表转移表检索的顺序值，以创建与第一信号表进行比较的第二信号表。 软件处理程序连续地执行从调用表和网表传送表检索的值，并比较第一和第二信号表，直到创建的第二信号表都与存储在存储器中的第一信号表相同。 软件处理装置还包括延迟顺序处理，直到用于将第二信号表与第一信号表进行比较的比较步骤达到稳定状态。

公开(公告)号：US5051938A

公开(公告)日：1991-09-24

申请号：US370896

申请日：1989-06-23

申请人： Stanley M. Hyduke

发明人： Stanley M. Hyduke

IPC分类号： G06F11/25 ,  G01R31/3183 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/318378 ,  G06F17/5022

摘要： A system and method for selectively simulating logic circuit designs in which a data tables generator receives information from a schematic entry program or netlist entry file and produces data tables for use by a simulator. A designer provides inputs to the data tables generator from a schematic entry program or a netlist entry file. The data tables generator generates from the information received a table of used integrated circuits and a table of their connections. A simulator then receives the output from the data tables generator and produces a design simulation program table that executes integrated circuit model subroutine stored in an integrated circuit model reference library and netlist subroutines stored in a netlist connectivity table. The system may also be used for testing logic circuits on a printed circuit board by capturing signals from a potentially defective logic section of the printed circuit board and feeding them into test points of the integrated circuit simulated by the computer simulator.

公开(公告)号：US5479355A

公开(公告)日：1995-12-26

申请号：US121926

申请日：1993-09-14

申请人： Stanley M. Hyduke

发明人： Stanley M. Hyduke

IPC分类号： G06F11/26 ,  G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/261

摘要： A system and method for a closed loop operation of computer-based designs with external electrical hardware. The system is comprised of a general purpose computer, schematic editor, real-time interactive design simulator, interface circuits and external electrical hardware. The simulator is responsive to the schematic editor and generates signals that are converted by an interface circuit to the signal format demanded by the external electrical hardware. The interface circuit also converts signals produced by the external electrical hardware to be compatible with the simulator format. The above system allows the real-time interactive design simulator and the external electrical hardware to interact with each other in a closed loop.

摘要翻译： 用于外部电气硬件的基于计算机的设计的闭环操作的系统和方法。 该系统由通用计算机，原理图编辑器，实时交互式设计仿真器，接口电路和外部电气硬件组成。 仿真器响应于原理图编辑器，并产生由接口电路转换为外部电气硬件所要求的信号格式的信号。 接口电路还将由外部电气硬件产生的信号转换成与模拟器格式兼容。 上述系统允许实时交互式设计模拟器和外部电气硬件在闭环中相互交互。

公开(公告)号：US4791357A

公开(公告)日：1988-12-13

申请号：US019641

申请日：1987-02-27

申请人： Stanley M. Hyduke

发明人： Stanley M. Hyduke

IPC分类号： G01R31/3193 ,  G01R31/28

CPC分类号： G01R31/31935

摘要： An Electronic Circuit testing system and method in which a test pattern is applied to an electronic circuit and captured by a sample capturing device. The test pattern is simultaneously applied to a functional schematic model of the electronic circuit under test and a calculated output signal representing the correct signal output of the electronic circuit is generated. The calculated output signal and the captured output signals are then compared to determine the signal changes for a given period of time. In comparing the two signals the number of transitions or tolerance differences of the two signals is determined and a malfunction in the signal is indicated by an excess of signal changes or tolerance differences. The method and the apparatus can also be applied to the design or a generation of electronic circuits.

摘要翻译： 一种电子电路测试系统和方法，其中将测试图案应用于电子电路并由样本捕获装置捕获。 测试模式同时应用于被测电子电路的功能示意模型，产生表示电子电路正确信号输出的计算输出信号。 然后将计算的输出信号和捕获的输出信号进行比较，以确定给定时间段内的信号变化。 在比较两个信号时，确定两个信号的转换或公差差的数量，并且信号的故障由信号变化或容差的过大表示。 该方法和装置还可以应用于电子电路的设计或生成。