公开(公告)号：US07797700B2

公开(公告)日：2010-09-14

申请号：US10831539

申请日：2004-04-23

Applicant: Frederic Robin ,  Alain Artieri ,  Stephane Audrain ,  Jacques Dumarest ,  Vincent Lefftz

Inventor： Frederic Robin ,  Alain Artieri ,  Stephane Audrain ,  Jacques Dumarest ,  Vincent Lefftz

IPC: G06F9/455 ,  G06F9/46 ,  G06K9/36 ,  H04N9/80 ,  H04N5/91 ,  H04N7/173

CPC classification number: G06F9/52 ,  H04N19/42

Abstract: Systems and methods are provided for processing different concurrent tasks by a subsystem managed by a central processor. Each tasks is comprised of successive messages including a first message, intermediate messages, and a last message. Each intermediate message comprises a subtask parameter and a link to the next message that indicates the time when the next message is to be processed. The central processor and the subsystem are connected to a storage memory and several counters associated with respective tasks. The system and method reduce task disruptions of the system.

Abstract translation: 提供了系统和方法，用于通过由中央处理器管理的子系统来处理不同的并发任务。 每个任务由包括第一消息，中间消息和最后消息的连续消息组成。 每个中间消息包括子任务参数和指向下一个消息的链接，指示下一个消息要被处理的时间。 中央处理器和子系统连接到存储存储器和与相应任务相关联的若干计数器。 系统和方法减少系统的任务中断。

公开(公告)号：US20050228969A1

公开(公告)日：2005-10-13

申请号：US11102604

申请日：2005-04-08

Applicant: Stephane Audrain ,  Jean-Marc Gentit

Inventor： Stephane Audrain ,  Jean-Marc Gentit

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/00 ,  G06F15/00 ,  G11C7/00

CPC classification number: G06F9/3802 ,  G06F9/30156 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/3822 ,  G06F9/3885

Abstract: An integrated circuit includes a processor and a program memory device on a common substrate. The memory device is able to deliver to the processor VLIW instructions with at least m operative fields. The memory device comprises: a dictionary memory comprising dictionary instructions each having at least m dictionary elementary instructions; an instructions memory having primary instructions each associated with a VLIW instruction and containing its data, the address of a dictionary instruction, and m masking bits; and m selection devices respectively controlled by the masking bits and each delivering either an NOP instruction, or the dictionary elementary instruction corresponding to the masking bit, so as to reconstruct, by combination with the data of the primary instruction, the VLIW instruction.

Abstract translation: 集成电路包括在公共基板上的处理器和程序存储器件。 存储器件能够至少在m个操作区域传送到处理器VLIW指令。 所述存储装置包括：字典存储器，包括每个具有至少m个字典基本指令的字典指令; 指令存储器，其具有每个与VLIW指令相关联并且包含其数据，字典指令的地址和m个掩蔽位的主指令; 以及分别由掩蔽位控制的m个选择装置，并且每个选择装置输送与所述屏蔽位相对应的NOP指令或字典基本指令，以便通过与主指令的数据组合来重建VLIW指令。