公开(公告)号：US5084411A

公开(公告)日：1992-01-28

申请号：US277593

申请日：1988-11-29

申请人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

发明人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

IPC分类号： H01L21/20 ,  H01L21/205

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0262 ,  Y10S148/015 ,  Y10S438/902

摘要： Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625.degree. and 825.degree. C.

摘要翻译： 根据以下发现提供了具有硅到SiGe合金异质结的改进的器件。 使用X射线形貌和透射电子显微镜来定量由作为化学气相沉积技术的限制反应处理（LRP）形成的生长的Si1-xGex膜中的失配位错间隔。 这些分析技术也用于研究在通过LRP和分子束外延（MBE）生长的材料退火期间的位错形成。 失配位错首先出现在生长材料中的厚度对于两种生长技术是相似的。 在625℃至1000℃的范围内快速热退火后，还研究了封盖和未封装的膜的热稳定性。在含有外延硅帽的样品中观察到不合适的位错显着更少。 在625°和825℃之间的温度下退火未封层后，观察到在CVD和MBE膜中产生的失配位错数量的一些差异。

公开(公告)号：US5256550A

公开(公告)日：1993-10-26

申请号：US715054

申请日：1991-06-12

申请人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

发明人： Stephen Laderman ,  Martin Scott ,  Theodore I. Kamins ,  Judy L. Hoyt ,  Clifford A. King ,  James F. Gibbons ,  David B. Noble

IPC分类号： H01L21/20 ,  H01L21/205

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/015 ,  Y10S438/902 ,  Y10S438/938

摘要： The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth. The composition of the third crystalline layer must be such that upon deposition or growth, the third layer substantially continuously binds to the heteroepitaxial structure of the second layer. Subsequent to growth of the at least three layer structure, the structure is processed at temperatures in excess of the growth temperature of the second heteroepitaxial layer. Presence of the third crystalline layer prevents the generation of a substantial amount of misfit dislocations between the first crystalline layer substrate and the second heteroepitaxial layer.

摘要翻译： 本发明包括一种在应变下使用至少一个异质外延层的器件和电路的制造方法。 基于先前已知的无盖层的平衡理论，异质外延层的厚度超过了在结晶衬底上的无盖异质外延层的计算的平衡临界厚度的两倍。 在异质外延层的生长之后，在高于异质外延层的生长温度的温度下处理该结构。 应变异质外延层（第二层）在第一底层晶体层的表面上外延生长，产生异质结。 随后，在第二应变异质外延层的主要暴露表面上沉积或生长第三晶体层。 第三晶体层的优选生长方式是外延生长。 第三结晶层的组成必须使得在沉积或生长时，第三层基本上连续地结合到第二层的异质外延结构。 在至少三层结构生长之后，在超过第二异质外延层的生长温度的温度下处理该结构。 第三结晶层的存在防止在第一晶体层衬底和第二异质外延层之间产生大量的失配位错。