公开(公告)号：US08927963B2

公开(公告)日：2015-01-06

申请号：US13512643

申请日：2011-06-30

Applicant: Zongliang Huo ,  Ming Liu

Inventor： Zongliang Huo ,  Ming Liu

IPC: H01L29/06 ,  H01L31/00 ,  H01L29/78

CPC classification number: H01L29/7841 ,  Y10S438/933 ,  Y10S438/938

Abstract: A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.

Abstract translation: 公开了半导体存储单元，半导体存储器件及其制造方法。 半导体存储单元可以包括：衬底; 衬底上的沟道区; 沟道区域上方的栅极区域; 源极区域和漏极区域，并且位于沟道区域的相对侧; 以及掩埋层，其设置在基板和沟道区域之间，并且包括具有比用于沟道区域材料的材料窄的带的禁带的材料。 掩埋层材料具有比沟道区域材料窄的禁带，使得在掩埋层中形成空穴阻挡层。 由于屏障，存储在掩埋层中的孔难以泄漏出来，导致利用浮体效应改善存储单元的信息保持持续时间。

公开(公告)号：US08906789B2

公开(公告)日：2014-12-09

申请号：US13873323

申请日：2013-04-30

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chun Hsiung Tsai ,  Yi-Fang Pai ,  Chien-Chang Su ,  Tzu-Chun Tseng ,  Meng-Yueh Liu

IPC: H01L21/00 ,  H01L29/78 ,  C30B25/16

CPC classification number: C30B25/165 ,  C30B25/16 ,  C30B29/06 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  Y10S438/938

Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.

Abstract translation: 本公开内容涉及通过不对称循环沉积蚀刻（CDE）外延形成外延层的方法。 设计CDE工艺的一个或多个循环的初始层生长速率以增强外延层的结晶质量。 外延材料的生长速率可以通过调节在外延生长发生的处理室内的一种或多种含硅前体的流速来改变。 还可以通过调节一种或多种蒸气蚀刻剂的温度或分压或处理室内的温度来改变蚀刻速率。 在一些实施例中，以低生长速率实现大于用于应变松弛的外延材料的临界厚度的初始层厚度，随后对于外延生长的其余部分具有高生长速率。 还公开了其它方法。

公开(公告)号：US20140295629A1

公开(公告)日：2014-10-02

申请号：US13850887

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

公开(公告)号：US08524012B2

公开(公告)日：2013-09-03

申请号：US13357432

申请日：2012-01-24

Applicant: Troy J. Baker ,  Benjamin A. Haskell ,  Paul T. Fini ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamua

Inventor： Troy J. Baker ,  Benjamin A. Haskell ,  Paul T. Fini ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamua

IPC: H01L21/205

CPC classification number: C30B29/406 ,  C30B25/02 ,  C30B25/18 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02658 ,  H01L33/007 ,  Y10S438/938

Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1011} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {1013} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {1122} gallium nitride (GaN) grown on a {1100} sapphire substrate, and (4) {1013} gallium nitride (GaN) grown on a {1100} sapphire substrate.

Abstract translation: 一种在杂交尖晶石衬底上生长平面，半极性氮化物膜的方法，其中大面积的平面半极性氮化物膜平行于衬底的表面。 平面膜和衬底是：（1）在{100}尖晶石衬底上在特定方向上生长的{1011}氮化镓（GaN），（2）在{110}尖晶石衬底上生长的{1013}氮化镓（GaN） ，（3）在{1100}蓝宝石衬底上生长的{1122}氮化镓（GaN），以及（4）在{1100}蓝宝石衬底上生长的{1013}氮化镓（GaN）。

公开(公告)号：US08502283B2

公开(公告)日：2013-08-06

申请号：US11926655

申请日：2007-10-29

Applicant: Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US20120199849A1

公开(公告)日：2012-08-09

申请号：US13446124

申请日：2012-04-13

Applicant: Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

Inventor： Chen-Hua Tsai ,  Bang-Chiang Lan ,  Yu-Hsin Lin ,  Yi-Cheng Liu ,  Cheng-Tzung Tsai

IPC: H01L29/161 ,  H01L29/772

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S438/931 ,  Y10S438/933 ,  Y10S438/938

Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

Abstract translation: 制造金属氧化物半导体场效应晶体管的方法包括首先提供其上形成有栅极结构的衬底。 之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹槽。 另外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。 随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。 另外，源极/漏极层沉积在第二凹部中。 由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

公开(公告)号：US08232581B2

公开(公告)日：2012-07-31

申请号：US12822944

申请日：2010-06-24

Applicant: Geoffrey Pourtois ,  Clement Merckling ,  Guy Brammertz ,  Matty Caymax

Inventor： Geoffrey Pourtois ,  Clement Merckling ,  Guy Brammertz ,  Matty Caymax

IPC: H01L29/20 ,  H01L21/203

CPC classification number: H01L21/02455 ,  H01L21/02387 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02535 ,  Y10S438/933 ,  Y10S438/938

Abstract: Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a or a crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.

Abstract translation: 制造III-V工程衬底涉及提供包括由具有<110>或<111>晶体取向的第一III-V化合物制成的上层的基底基底，形成中间层，该中间层至少包含第二 III-V族化合物，其中中间层覆盖并与基底基材的上层接触。 然后生长由IV族半导体材料制成的假型钝化层，使其与中间层重叠并接触。 这可以启用未打开的界面。 衬底表面可以更平滑，意味着较少的表面应力问题。 它可以用于诸如金属氧化物半导体场效应晶体管（MOSFET），高电子迁移率晶体管（HEMT），隧道场效应晶体管（TFET）和光电子器件的电子器件中。

公开(公告)号：US08227791B2

公开(公告)日：2012-07-24

申请号：US12693408

申请日：2010-01-25

Applicant: Chunhui Yan

Inventor： Chunhui Yan

IPC: H01L29/06

CPC classification number: H01L33/12 ,  H01L33/06 ,  H01L33/32 ,  Y10S438/938

Abstract: A strain balanced active-region design is disclosed for optoelectronic devices such as light-emitting diodes (LEDs) and laser diodes (LDs) for better device performance. Lying below the active-region, a lattice-constant tailored strain-balancing layer provides lattice template for the active-region, enabling balanced strain within the active-region for the purposes of 1) growing thick, multiple-layer active-region with reduced defects, or 2) engineering polarization fields within the active-region for enhanced performance. The strain-balancing layer in general enlarges active-region design and growth windows. In some embodiments of the present invention, the strain-balancing layer is made of quaternary InxAlyGa1-x-yN (0≦x≦1, 0≦y≦1, x+y≦1), whose lattice-constant is tailored to exert opposite strains in adjoining layers within the active-region. A relaxation-enhancement layer can be provided beneath the strain-balancing layer for enhancing the relaxation of the strain-balancing layer.

Abstract translation: 公开了用于诸如发光二极管（LED）和激光二极管（LD）的光电子器件的应变平衡有源区设计，以获得更好的器件性能。 在活性区域之下，晶格常数量身定制的应变平衡层为活性区域提供晶格模板，使活性区域内的平衡应变达到目的1）生长厚的多层活性区域，减少 缺陷，或2）在活动区域​​内设计极化场，以提高性能。 应变平衡层通常扩大了主动区域设计和增长窗口。 在本发明的一些实施例中，应变平衡层由其晶格常数被定制以施加的四元In x Al y Ga 1-x-y N（0＆lt; n 1; x＆n 1; 1，x 1和y 1; 在活性区域内相邻层的相反应变。 可以在应变平衡层的下方设置松弛增强层，以增强应变平衡层的松弛。

公开(公告)号：US08120065B2

公开(公告)日：2012-02-21

申请号：US12541763

申请日：2009-08-14

Applicant: Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

Inventor： Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

IPC: H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848 ,  Y10S438/933 ,  Y10S438/938

Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.

Abstract translation: 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。

公开(公告)号：US08110478B2

公开(公告)日：2012-02-07

申请号：US12253301

申请日：2008-10-17

Applicant: Shunpei Yamazaki ,  Hideto Ohnuma ,  Jun Koyama

Inventor： Shunpei Yamazaki ,  Hideto Ohnuma ,  Jun Koyama

IPC: H01L21/76

CPC classification number: H01L27/1266 ,  C03C17/3435 ,  C03C17/3482 ,  C03C2218/32 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772 ,  Y10S438/938 ,  Y10S438/961

Abstract: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate.

Abstract translation: 如果附着的单晶硅层的尺寸不合适，即使使用大的玻璃基板，也不能使要获得的面板的数量最大化。 因此，在本发明中，从大致圆形的单晶半导体晶片形成大致四边形的单晶半导体基板，通过将离子束照射到单晶半导体基板中形成损伤层。 多个单晶半导体基板被布置成在支撑基板的一个表面上彼此分离。 通过热处理，在损伤层中产生裂纹，并且单个半导体衬底被分离，而单个半导体层留在支撑衬底上。 之后，从结合到支撑基板的单晶半导体层制造一个或多个显示面板。