公开(公告)号：US20050278664A1

公开(公告)日：2005-12-15

申请号：US10855725

申请日：2004-05-27

申请人： Rajat Chaudhry ,  Sang Dhong ,  Stephen Posluszny ,  Daniel Stasiak

发明人： Rajat Chaudhry ,  Sang Dhong ,  Stephen Posluszny ,  Daniel Stasiak

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5022

摘要： A method, an apparatus, and a computer program are provided for predicting power consumption for chip. The model for predicting power consumptions is modified so at to provide a high degree of accuracy with a minimal amount of computing time. Traditionally, when modeling a chip, a vast amount of time and computer resources were required to predict power consumption. Techniques required less time and less computer power, but the accuracy also decreased. However, by breaking down a chip into macros and developing energy rules for each macro, simple techniques can be employed to accurately predict power consumption under real world conditions with a minimal amount of time and computing power.

摘要翻译： 提供了一种用于预测芯片功耗的方法，装置和计算机程序。 修改用于预测功耗的模型，以便以最小的计算时间提供高精度。 传统上，当对芯片建模时，需要大量的时间和计算机资源来预测功耗。 技术需要更少的时间和更少的计算机功率，但精度也降低了。 然而，通过将芯片分解成宏并为每个宏开发能量规则，可以采用简单的技术来以最小的时间和计算能力精确地预测现实世界条件下的功耗。

公开(公告)号：US20050055185A1

公开(公告)日：2005-03-10

申请号：US10971851

申请日：2004-10-22

申请人： Sang Dhong ,  Harm Hofstee ,  Kevin Nowka ,  Stephen Posluszny ,  Joel Silberman

发明人： Sang Dhong ,  Harm Hofstee ,  Kevin Nowka ,  Stephen Posluszny ,  Joel Silberman

IPC分类号： G06F7/38 ,  G06F7/42 ,  G06F7/485 ,  G06F7/499 ,  G06F17/10

CPC分类号： G06F7/485 ,  G06F7/49947

摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

摘要翻译： 一种用于对浮点操作数进行相加和相乘以产生固定大小的尾数结果的方法和装置。 根据本加法，第一浮点数操作数的尾数根据相对操作数指数信息移位。 接下来，将第一操作数尾数添加到第二操作数尾数。 所述添加步骤包括用随机生成的进位位替换第一操作数尾数的最不重要的非重叠部分。 根据乘法方法，从一对浮点运算符尾数生成部分乘积数组。 接下来，在将部分乘积阵列压缩为压缩尾数结果之前，将部分乘积阵列的低阶位部分替换为随机生成的进位值。