公开(公告)号：US20050278664A1

公开(公告)日：2005-12-15

申请号：US10855725

申请日：2004-05-27

申请人： Rajat Chaudhry ,  Sang Dhong ,  Stephen Posluszny ,  Daniel Stasiak

发明人： Rajat Chaudhry ,  Sang Dhong ,  Stephen Posluszny ,  Daniel Stasiak

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5022

摘要： A method, an apparatus, and a computer program are provided for predicting power consumption for chip. The model for predicting power consumptions is modified so at to provide a high degree of accuracy with a minimal amount of computing time. Traditionally, when modeling a chip, a vast amount of time and computer resources were required to predict power consumption. Techniques required less time and less computer power, but the accuracy also decreased. However, by breaking down a chip into macros and developing energy rules for each macro, simple techniques can be employed to accurately predict power consumption under real world conditions with a minimal amount of time and computing power.

摘要翻译： 提供了一种用于预测芯片功耗的方法，装置和计算机程序。 修改用于预测功耗的模型，以便以最小的计算时间提供高精度。 传统上，当对芯片建模时，需要大量的时间和计算机资源来预测功耗。 技术需要更少的时间和更少的计算机功率，但精度也降低了。 然而，通过将芯片分解成宏并为每个宏开发能量规则，可以采用简单的技术来以最小的时间和计算能力精确地预测现实世界条件下的功耗。

公开(公告)号：US20050055185A1

公开(公告)日：2005-03-10

申请号：US10971851

申请日：2004-10-22

申请人： Sang Dhong ,  Harm Hofstee ,  Kevin Nowka ,  Stephen Posluszny ,  Joel Silberman

发明人： Sang Dhong ,  Harm Hofstee ,  Kevin Nowka ,  Stephen Posluszny ,  Joel Silberman

IPC分类号： G06F7/38 ,  G06F7/42 ,  G06F7/485 ,  G06F7/499 ,  G06F17/10

CPC分类号： G06F7/485 ,  G06F7/49947

摘要： A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first floating-point operand is shifted in accordance with relative operand exponent information. Next, the first operand mantissa is added to the second operand mantissa. The addition step includes replacing a least significant non-overlapped portion of the first operand mantissa with a randomly-generated carry-in bit. In accordance with the multiplication method, a partial product array is generated from a pair of floating-point operand mantissas. Next, prior to compressing the partial product array into a compressed mantissa result, a lower-order bit portion of the partial product array is replaced with a randomly generated carry-in value.

摘要翻译： 一种用于对浮点操作数进行相加和相乘以产生固定大小的尾数结果的方法和装置。 根据本加法，第一浮点数操作数的尾数根据相对操作数指数信息移位。 接下来，将第一操作数尾数添加到第二操作数尾数。 所述添加步骤包括用随机生成的进位位替换第一操作数尾数的最不重要的非重叠部分。 根据乘法方法，从一对浮点运算符尾数生成部分乘积数组。 接下来，在将部分乘积阵列压缩为压缩尾数结果之前，将部分乘积阵列的低阶位部分替换为随机生成的进位值。

公开(公告)号：US20070043895A1

公开(公告)日：2007-02-22

申请号：US11204417

申请日：2005-08-16

申请人： Chad Adams ,  Toru Asano ,  Sang Dhong ,  Takaaki Nakazato ,  Joel Silberman ,  Osamu Takahashi

发明人： Chad Adams ,  Toru Asano ,  Sang Dhong ,  Takaaki Nakazato ,  Joel Silberman ,  Osamu Takahashi

IPC分类号： G06F12/06 ,  G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3275 ,  G11C8/08 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/152

摘要： An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.

摘要翻译： 提供了一种装置，方法和计算机程序以有效地使用微处理器阵列。 通常，微处理器阵列可以分为多个子阵列。 此外，在常规阵列中，当使用微处理器阵列时，每个子阵列被接合。 为了减轻微处理器阵列消耗的功率，采用行选择逻辑仅与特定的子阵列相啮合。 因此，省去了未使用的亚军消耗的电力。

公开(公告)号：US20060101315A1

公开(公告)日：2006-05-11

申请号：US10982111

申请日：2004-11-05

申请人： Sang Dhong ,  Hwa-Joon Oh ,  Silvia Mueller ,  Joel Silberman

发明人： Sang Dhong ,  Hwa-Joon Oh ,  Silvia Mueller ,  Joel Silberman

IPC分类号： G01R31/28

CPC分类号： G06F11/267 ,  G01R31/3008

摘要： An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.

摘要翻译： 提供了一种装置，方法和计算机程序以减少处理器中的泄漏电流。 传统上，采用额外的逻辑来减少漏电流。 然而，减少漏电流而不牺牲精细的晶粒操作和速度可能是困难的。 可以通过将多路复用器（多路复用器）复用到扫描寄存器的扫描路径中来实现这一目标，从而可以单独关闭处理器的单元或子单元。 此外，多路复用器并不并入时间路径，因此可以保留速度。

公开(公告)号：US07724567B2

公开(公告)日：2010-05-25

申请号：US12167821

申请日：2008-07-03

申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

IPC分类号： G11C11/36

CPC分类号： G11C15/04 ,  G06F12/0864 ,  G06F12/0895 ,  G11C11/39

摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

摘要翻译： 内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。 第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平 匹配检测操作。 内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

公开(公告)号：US20100002482A1

公开(公告)日：2010-01-07

申请号：US12167823

申请日：2008-07-03

申请人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

发明人： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C11/39

摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.

摘要翻译： 内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。 第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平 匹配检测操作。 内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

公开(公告)号：US20060101108A1

公开(公告)日：2006-05-11

申请号：US10982119

申请日：2004-11-05

申请人： Sang Dhong ,  Christian Jacobi ,  Silvia Mueller ,  Hwa-Joon Oh ,  Yonetaro Totsuka

发明人： Sang Dhong ,  Christian Jacobi ,  Silvia Mueller ,  Hwa-Joon Oh ,  Yonetaro Totsuka

IPC分类号： G06F7/50

CPC分类号： G06F7/49952 ,  G06F7/483

摘要： A method, an apparatus, and a computer program are provided to more efficiently generate a sticky bit in a Floating Point Design. Traditionally, separate ORing logic or OR trees were employed to compress the stick outputs of a normalization shifter into at least one sticky bit. However, this design has power consumption and area costs associated with it. To overcome these disadvantages, the OR trees of Leading Zero Counters (CLZs) are employed in conjunction with the Edge Vector logic of a Leading Sign Anticipator and an additional OR gate to determine the sticky bit.

摘要翻译： 提供了一种方法，装置和计算机程序，以在浮点设计中更有效地生成粘性位。 传统上，使用单独的ORing逻辑或OR树来将归一化移位器的棒输出压缩成至少一个粘性位。 但是，该设计具有与之相关的功耗和面积成本。 为了克服这些缺点，领先的零计数器（CLZ）的OR树结合领先标志预期者的边缘向量逻辑和附加的或门来确定粘滞位。

公开(公告)号：US20060097766A1

公开(公告)日：2006-05-11

申请号：US10982112

申请日：2004-11-05

申请人： Sang Dhong ,  Joel Silberman ,  Osamu Takahashi

发明人： Sang Dhong ,  Joel Silberman ,  Osamu Takahashi

IPC分类号： H03K3/12

CPC分类号： H03K3/356113 ,  G01R31/318541

摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.

摘要翻译： 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

公开(公告)号：US20060083101A1

公开(公告)日：2006-04-20

申请号：US10965627

申请日：2004-10-14

申请人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

发明人： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

IPC分类号： G11C8/00

CPC分类号： G11C8/06

摘要： An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.

公开(公告)号：US20050264324A1

公开(公告)日：2005-12-01

申请号：US10852863

申请日：2004-05-25

申请人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

发明人： Takaaki Nakazato ,  Toru Asano ,  Osamu Takahashi ,  Sang Dhong

IPC分类号： G11C11/419 ,  G11C7/06 ,  H03F3/45 ,  H03K3/012 ,  H03K3/356

CPC分类号： H03K3/012 ,  G11C7/065 ,  H03K3/356139

摘要： Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.

摘要翻译： 用于通过将这些晶体管的主体连接到除地之外的电压来增加可以流过读出放大器中的数据线下拉晶体管的电流量的系统和方法。 在一个实施例中，读出放大器中的数据线下拉晶体管的主体被连接到读出放大器的相对侧上的中间节点，以增加通过数据线下拉晶体管的电流，并且还减少 通过位线晶体管的动作将中间节点处的电压拉低。 在一个实施例中，读出放大器还包括将中间节点预充电到未被下拉晶体管的阈值电压降低的预定电压的预充电电路。