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公开(公告)号:US20120117327A1
公开(公告)日:2012-05-10
申请号:US12941105
申请日:2010-11-08
申请人: Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
发明人: Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
IPC分类号: G06F12/08
CPC分类号: G06F9/3844
摘要: Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.
摘要翻译: 具有分支预测支持的每个分支指令在分支指令中的架构指定的位位置具有分支预测位。 指令高速缓存支持使用在分支指令执行时动态确定的更新的分支预测位修改分支指令。
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公开(公告)号:US20120017214A1
公开(公告)日:2012-01-19
申请号:US12837572
申请日:2010-07-16
IPC分类号: G06F9/46
CPC分类号: G06F9/3851 , G06F9/30123 , G06F9/30134 , G06F9/3806
摘要: A system and method of managing a stack shared by multiple threads of a processor includes allocating a first portion of a shared stack to a first thread and allocating a second portion of the shared stack to a second thread.
摘要翻译: 管理由处理器的多个线程共享的堆栈的系统和方法包括将共享堆栈的第一部分分配给第一线程,并将共享堆栈的第二部分分配给第二线程。
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公开(公告)号:US09122486B2
公开(公告)日:2015-09-01
申请号:US12941105
申请日:2010-11-08
申请人: Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
发明人: Suresh K. Venkumahanti , Lucian Codrescu , Stephen R. Shannon , Lin Wang , Phillip M. Jones , Daisy T. Palal , Jiajin Tu
CPC分类号: G06F9/3844
摘要: Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.
摘要翻译: 具有分支预测支持的每个分支指令在分支指令中的架构指定的位位置具有分支预测位。 指令高速缓存支持使用在分支指令执行时动态确定的更新的分支预测位修改分支指令。
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公开(公告)号:US20090249048A1
公开(公告)日:2009-10-01
申请号:US12057543
申请日:2008-03-28
IPC分类号: G06F9/32
CPC分类号: G06F9/3806 , G06F9/322
摘要: A data processing system includes a branch target buffer (BTB) including a plurality of entries, each entry comprising a tag portion and a long branch indicator. The system also includes segment target address storage circuitry which stores a plurality of segment target addresses, index storage circuitry which stores a plurality of indices for indexing into the segment target address storage circuitry, and control circuitry which receives an instruction address and determines whether the instruction address matches a valid entry in the BTB. When the instruction address matches a valid entry in the BTB and the long branch indicator of the valid entry indicates a long branch, the index storage circuitry provides a selected index of the plurality of indices selected by the received instruction address. In response to the selected index, the segment target address storage circuitry provides a selected segment target address as a higher order target address portion.
摘要翻译: 数据处理系统包括包括多个条目的分支目标缓冲器(BTB),每个条目包括标签部分和长分支指示符。 该系统还包括存储多个分段目标地址的分段目标地址存储电路,索引存储电路,其存储用于索引到分段目标地址存储电路中的多个索引;以及控制电路,其接收指令地址并确定该指令 地址匹配BTB中的有效条目。 当指令地址与BTB中的有效条目匹配,并且有效条目的长分支指示符指示长分支时,索引存储电路提供由接收到的指令地址选择的多个索引的选定索引。 响应于所选择的索引,分段目标地址存储电路将所选择的分段目标地址提供为较高阶目标地址部分。
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