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公开(公告)号：US09432388B2
公开(公告)日：2016-08-30
申请号：US13446182
申请日：2012-04-13
CPC分类号： H04L65/605 , H04L43/12 , H04L63/00 , H04L63/1425 , H04L63/30 , H04L65/1006 , H04L65/104 , H04L67/42 , H04M3/2281 , H04M3/42221 , H04M3/51
摘要： A communication system including a media server through which communication packets are exchanged for recording and monitoring purposes is disclosed. A tap is associated with each communication endpoint allowing for cradle to grave recording of communications despite their subsequent routing or branching. An incoming communication is routed to a first tap and upon selection of a receiving party; the first tap is routed to a second tap which forwards communication packets on to the receiving party. The taps may be used to forward communication packets to any number of other taps or destinations, such as a recording device, monitoring user, or other user in the form of a conference.
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公开(公告)号：US09213665B2
公开(公告)日：2015-12-15
申请号：US12259368
申请日：2008-10-28
CPC分类号： G06F13/4217 , G06F9/3004 , G06F9/30043 , G06F9/3834 , G06F9/3885 , G06F13/16 , G06F2213/0054
摘要： A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.
摘要翻译： 具有处理器和目标设备的数据处理系统处理装饰指令（即具有装饰值的指令）。 诸如处理器之类的数据处理系统的设备通过系统互连将事务发送到目标设备。 装饰存储通知（DSN）事务包括指令操作的指示，与指令操作相关联的地址和装饰值（即，除了存储或负载之外还执行功能的目标设备的命令）。 系统互连上的事务包括地址阶段和数据阶段，从而提高系统带宽。 在一种形式中，目标设备（例如具有除了存储功能之外的功能的存储器）使用目标设备的存储位置处的信息执行读取 - 修改 - 写入操作。
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3.发明授权Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition 有权当竞争性指令完成执行以确保安全的共享资源状况时，指示禁用线程到其他线程公开(公告)号：US09047079B2
公开(公告)日：2015-06-02
申请号：US13435123
申请日：2012-03-30
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857 , G06F9/3889
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译： 用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找， 处理器核心内的缓冲区。 来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。 在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。 然后控制逻辑更新线程状态以指示线程被禁用。
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4.发明授权System and method for processing potentially self-inconsistent memory transactions 有权用于处理可能自不一致内存事务的系统和方法公开(公告)号：US09026742B2
公开(公告)日：2015-05-05
申请号：US11962331
申请日：2007-12-21
CPC分类号： G06F12/0828 , G06F12/0831 , G06F2212/1016 , G06F2212/507
摘要： A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.
摘要翻译： 处理器为与存储器请求相关联的一致性粒子提供存储器请求和一致性状态值。 所述处理器还根据所述一致性状态值是否表示所述处理器的多个高速缓存的累积一致性状态，还提供第一指示符或第二指示符。 第一指示符和第二指示符分别表示相关性状态值，表示累积相关性状态或潜在的非累积一致性状态。 如果提供了第二指示符，则事务管理模块响应于接收到第二指示符来确定是否请求相关性颗粒的累积一致性状态。 响应于确定请求累积一致性状态，事务管理模块向处理器提供对累积一致性状态的请求的指示符。 否则，事务管理模块处理存储器事务而不请求累积一致性状态。
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5.发明授权公开(公告)号：US08972671B2
公开(公告)日：2015-03-03
申请号：US11748350
申请日：2007-05-14
CPC分类号： G06F12/0831 , G06F11/3656
摘要： A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system.
摘要翻译： 描述了多个新的窥探事务类型。 一些请求中包含地址信息，其他包括请求中的缓存条目信息。 一些响应包括标签地址信息，有些则没有。 一些在事务的数据部分期间在数据总线上提供标签地址内容。 这些新的侦听事务类型在数据处理系统的调试过程中非常有用。
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公开(公告)号：US08041901B2
公开(公告)日：2011-10-18
申请号：US11682058
申请日：2007-03-05
申请人： Michael D. Snyder
发明人： Michael D. Snyder
IPC分类号： G06F12/00
CPC分类号： G06F11/3471 , G06F11/3466 , G06F2201/81 , G06F2201/86 , G06F2201/88
摘要： A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events.
摘要翻译： 公开了一种性能监视装置和方法。 该设备监视处理器的性能事件。 响应于特定演出事件的发生而调整计数器。 计数器可以与特定指令地址范围或数据地址范围相关联，使得仅当在指令地址范围或数据地址范围发生性能事件时才调整计数器。 因此，可以分析存储在计数器中的信息，以确定特定指令地址范围或数据地址范围是否导致特定的性能事件。 可以使用多个计数器，每个计数器与不同的性能事件，指令地址范围或数据地址范围相关联，以便对程序的哪些部分导致特定的性能事件进行详细分析。
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公开(公告)号：US07941499B2
公开(公告)日：2011-05-10
申请号：US11682867
申请日：2007-03-06
IPC分类号： G06F15/167
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译： 一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。 该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器内消息信息。 系统包括一致性互连和处理器。 处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。 该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息来生成中断。
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8.发明授权Interrupt controller for accelerated interrupt handling in a data processing system and method thereof 有权用于数据处理系统中加速中断处理的中断控制器及其方法公开(公告)号：US07849247B2
公开(公告)日：2010-12-07
申请号：US12250682
申请日：2008-10-14
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.
摘要翻译： 数据处理系统具有中断控制器，其向处理器提供中断请求以及对应的中断标识符和相应的中断向量。 如果处理器接受中断，处理器将通过中断标识符和中断确认返回相同的中断标识符值给中断控制器。 还可以提供中断/未采取的指示符。 用于协调中断控制器和处理器之间的中断处理的通信接口可能是异步的。
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9.发明授权Multiple address and arithmetic bit-mode data processing device and methods thereof 有权多地址和算术位模式数据处理装置及其方法公开(公告)号：US07805581B2
公开(公告)日：2010-09-28
申请号：US11679590
申请日：2007-02-27
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/30014 , G06F9/30189 , G06F9/342
摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.
摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。
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公开(公告)号：US20090323446A1
公开(公告)日：2009-12-31
申请号：US12164755
申请日：2008-06-30
申请人： SHAYAN ZHANG , JACK M. HIGMAN , MICHAEL D. SNYDER
发明人： SHAYAN ZHANG , JACK M. HIGMAN , MICHAEL D. SNYDER
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/026 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.
摘要翻译： 用于确定存储器是否能够在较低工作电压下工作的测试电路。 测试电路包括与存储器的其它读出放大器电路相比具有延迟的感测特性的感测电路。 利用该电路，测试电路可以确定感测电路是否可以在更严格的感测条件下提供有效的数据。 在一个示例中，感测电路在感测使能信号路径中包括延迟电路。 如果感测电路可以在更多的服务器操作条件下提供数据，则可以降低存储器工作电压。
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