DESIGN STRUCTURE FOR IN-SYSTEM REDUNDANT ARRAY REPAIR IN INTEGRATED CIRCUITS
    1.
    发明申请
    DESIGN STRUCTURE FOR IN-SYSTEM REDUNDANT ARRAY REPAIR IN INTEGRATED CIRCUITS 失效
    集成电路系统冗余阵列修复的设计结构

    公开(公告)号:US20080062783A1

    公开(公告)日:2008-03-13

    申请号:US11851613

    申请日:2007-09-07

    IPC分类号: G11C29/00 G11C17/18

    CPC分类号: G11C29/4401 G11C29/802

    摘要: A design structure for repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

    摘要翻译: 一种用于修复包括多个存储器阵列的类型的集成电路的设计结构和用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该设计结构为集成电路提供了一个控制数据选择器,用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源,集成电路外部; 并将替代控制数据源连接到控制数据选择器。 设计结构还通过控制数据选择器将来自其源的备用控制数据传递到存储器阵列,以控制存储器阵列的冗余逻辑。

    METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS
    2.
    发明申请
    METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS 有权
    用于集成电路系统冗余阵列维修的方法和装置

    公开(公告)号:US20080080274A1

    公开(公告)日:2008-04-03

    申请号:US11872088

    申请日:2007-10-15

    IPC分类号: G11C29/00

    CPC分类号: G11C29/4401 G11C29/802

    摘要: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

    摘要翻译: 公开了一种修复包括多个存储器阵列的类型的集成电路的方法,以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该方法包括以下步骤:向集成电路提供控制数据选择器,用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源,集成电路外部; 并将替代控制数据源连接到控制数据选择器。 该方法还包括在给定时间,通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。

    METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS
    4.
    发明申请
    METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS 失效
    用于集成电路系统冗余阵列维修的方法和装置

    公开(公告)号:US20070258296A1

    公开(公告)日:2007-11-08

    申请号:US11418052

    申请日:2006-05-04

    IPC分类号: G11C29/00 G11C7/00

    CPC分类号: G11C29/4401 G11C29/802

    摘要: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

    摘要翻译: 公开了一种修复包括多个存储器阵列的类型的集成电路的方法,以及用于控制用于控制阵列的冗余逻辑的控制数据的保险丝盒。 该方法包括以下步骤:向集成电路提供控制数据选择器,用于将控制数据从保险丝盒传送到存储器阵列; 提供备用控制数据源,集成电路外部; 并将替代控制数据源连接到控制数据选择器。 该方法还包括在给定时间,通过控制数据选择器将备用控制数据从其源传递到存储器阵列以控制存储器阵列的冗余逻辑的步骤。

    Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features
    5.
    发明申请
    Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features 失效
    用于定制和监控多个接口并实现增强的容错和隔离功能的方法和设备

    公开(公告)号:US20050204216A1

    公开(公告)日:2005-09-15

    申请号:US10798912

    申请日:2004-03-11

    CPC分类号: G01R31/318563

    摘要: A method and apparatus are provided for customizing and monitoring multiple interfaces, such as, multiple IEEE 1149.1 standard joint test access group (JTAG) interfaces and implementing enhanced fault tolerance and isolation features. A first interface is connected to a pair of master sources. A second interface is connected to a plurality of target interfaces; and a third interface is provided for a plurality of predefined control signals. A pair of redundant selectors is provided for coupling a select signal to the first multiplexer for selecting one of the plurality of target interfaces. A pair of redundant ATTENTION monitor functions is provided for monitoring ATTENTION signals for each of the plurality of target interfaces

    摘要翻译: 提供了一种方法和装置,用于定制和监视多个接口,例如多个IEEE 1149.1标准联合测试接入组(JTAG)接口,并实现增强的容错和隔离特性。 第一个接口连接到一对主源。 第二接口连接到多个目标接口; 并且为多个预定义的控制信号提供第三接口。 提供一对冗余选择器,用于将选择信号耦合到第一多路复用器,用于选择多个目标接口之一。 提供了一对冗余注意监视功能,用于监视多个目标接口中的每一个的“注意”信号