公开(公告)号：US07716514B2

公开(公告)日：2010-05-11

申请号：US11533065

申请日：2006-09-19

申请人： Steven John Baumgartner ,  Charles Porter Geer

发明人： Steven John Baumgartner ,  Charles Porter Geer

IPC分类号： G06F1/00 ,  G06F1/24 ,  H04L25/40

CPC分类号： G06F1/12

摘要： An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

摘要翻译： 描述了用于以最小的等待时间来在独立时钟域中动态地对准时钟的装置和方法。 在优选实施例中，目的时钟域中的目的时钟域的数据时钟的多倍的参考时钟用于从源域采样数据采样信号。 采样数据用于确定数据采样信号在什么时间片上参考时钟信号正在改变，因此在数据时钟的时间片或相位的什么阶段可以对准时钟，以确保有效数据将在时钟域之间传输 。

公开(公告)号：US06771694B1

公开(公告)日：2004-08-03

申请号：US09614515

申请日：2000-07-12

申请人： Steven John Baumgartner

发明人： Steven John Baumgartner

IPC分类号： H04B138

CPC分类号： H04L1/0002 ,  H04B1/38 ,  H04B10/40 ,  H04L5/1446

摘要： An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.

公开(公告)号：US06658030B1

公开(公告)日：2003-12-02

申请号：US09618221

申请日：2000-07-18

申请人： Steven John Baumgartner ,  Daniel Scott Hedin ,  Matthew James Paschal

发明人： Steven John Baumgartner ,  Daniel Scott Hedin ,  Matthew James Paschal

IPC分类号： H01S313

CPC分类号： H04B10/032 ,  H04J14/0221

摘要： A method and apparatus are provided to ensure that laser optical power does not exceed a “safe” level in an open loop parallel optical link in the event that a fiber optic ribbon cable is broken or otherwise severed. A duplex parallel optical link includes a transmitter and receiver pair and a fiber optic ribbon that includes a designated number of channels that cannot be split. The duplex transceiver includes a corresponding transmitter and receiver that are physically attached to each other and cannot be detached therefrom, so as to ensure safe, laser optical power in the event that the fiber optic ribbon cable is broken or severed. Safe optical power is ensured by redundant current and voltage safety checks.

摘要翻译： 提供一种方法和装置，以确保在光纤带状电缆断裂或以其他方式切断的情况下，开环并联光链路中的激光光功率不超过“安全”水平。 双工并行光链路包括发射机和接收机对以及包括指定数量的不能分裂的信道的光纤带。 双工收发器包括物理上彼此连接并且不能从其分离的相应发射器和接收器，以便在光纤带状电缆断裂或断开的情况下确保安全的激光光功率。 通过冗余电流和电压安全检查确保安全光功率。

公开(公告)号：US06532245B1

公开(公告)日：2003-03-11

申请号：US09429280

申请日：1999-10-28

申请人： Matthew James Paschal ,  Steven John Baumgartner

发明人： Matthew James Paschal ,  Steven John Baumgartner

IPC分类号： H01S300

CPC分类号： H01S5/0427 ,  H01S5/183

摘要： A laser driver, e.g., a vertical cavity surface emitting laser (VCSEL) driver, with low duty cycle distortion is provided. An fT doubler circuit, used as the driver input, has two current sources, and reduces parasitic capacitance which can cause duty cycle distortion. The current sources may be analog or digital sources, the latter being digitally adjustable to provide for digital modulation adjustment. A current mirror circuit with a reference current source is provided for the two current sources.

摘要翻译： 提供了具有低占空比失真的激光驱动器，例如垂直腔表面发射激光器（VCSEL）驱动器。 用作驱动器输入的fT倍频电路具有两个电流源，并减少可能导致占空比失真的寄生电容。 电流源可以是模拟或数字源，后者可数字调节以提供数字调制调整。 为两个电流源提供了具有参考电流源的电流镜电路。

公开(公告)号：US06177815B1

公开(公告)日：2001-01-23

申请号：US09396989

申请日：1999-09-15

申请人： Steven John Baumgartner ,  Anh Duy Ngo ,  David Warren Siljenberg

发明人： Steven John Baumgartner ,  Anh Duy Ngo ,  David Warren Siljenberg

IPC分类号： H03K522

CPC分类号： H03K5/153 ,  G01R19/155 ,  G01R19/1659

摘要： A improved signal detector is provided. The signal detector includes a linear amplifier receiving the input signal and providing an amplified signal. A full-wave rectifier is coupled to the linear amplifier and provides a rectified signal. A low-pass filter is coupled to the full-wave rectifier receiving the rectified signal and providing a comparing signal. A high threshold reference and a low threshold reference respectively is applied to a first comparator and a second comparator, each receiving the comparing signal. The first comparator and the second comparator respectively provide a first compared signal and a second compared signal. A reference path providing the high threshold reference and the low threshold reference includes a linear amplifier, a full-wave rectifier and a low-pass filter providing the high threshold reference. A linear charge pump is connected at its input to the linear amplifier and connected at its output to a low-pass filter to provide the low threshold reference.

摘要翻译： 提供改进的信号检测器。 信号检测器包括接收输入信号并提供放大信号的线性放大器。 全波整流器耦合到线性放大器并提供整流信号。 低通滤波器耦合到接收整流信号的全波整流器并提供比较信号。 分别将高阈值参考值和低阈值参考值应用于每个接收比较信号的第一比较器和第二比较器。 第一比较器和第二比较器分别提供第一比较信号和第二比较信号。 提供高阈值参考和低阈值参考的参考路径包括线性放大器，全波整流器和提供高阈值参考的低通滤波器。 线性电荷泵在其输入端连接到线性放大器，并在其输出端连接到低通滤波器以提供低阈值参考。

公开(公告)号：US07945805B2

公开(公告)日：2011-05-17

申请号：US11930345

申请日：2007-10-31

申请人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

发明人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

IPC分类号： G06F1/10

CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

摘要翻译： 用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。 在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

公开(公告)号：US07904741B2

公开(公告)日：2011-03-08

申请号：US11870985

申请日：2007-10-11

申请人： Steven John Baumgartner ,  Charles Porter Geer

发明人： Steven John Baumgartner ,  Charles Porter Geer

IPC分类号： G06F1/00 ,  G06F1/24 ,  G06F1/12

CPC分类号： G06F1/12

摘要： A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

摘要翻译： 描述了一种设计结构，用于以最小的延迟动态地对齐独立时钟域中的时钟。 在优选实施例中，目的时钟域中的目的时钟域的数据时钟的多倍的参考时钟用于从源域采样数据采样信号。 采样数据用于确定数据采样信号在什么时间片上参考时钟信号正在改变，因此在数据时钟的时间片或相位的什么阶段可以对准时钟，以确保有效数据将在时钟域之间传输 。

公开(公告)号：US07624297B2

公开(公告)日：2009-11-24

申请号：US11610063

申请日：2006-12-13

申请人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

发明人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

IPC分类号： G06F1/10

CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

摘要： A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

摘要翻译： 高速计算机处理器系统包括用于图形处理器的高速接口。 在优选实施例中，高速接口包括与图形处理器上的类似高速接口相连接的前端总线（FSB）。

公开(公告)号：US20080147952A1

公开(公告)日：2008-06-19

申请号：US11610063

申请日：2006-12-13

申请人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

发明人： Steven John Baumgartner ,  Anthony Richard Bonaccio ,  Timothy Clyde Buchholtz ,  Daniel Mark Dreps ,  Charles Porter Geer ,  Mounir Meghelli ,  Sergey Vladimirovich Rylov ,  David W. Siljenberg ,  Dana Marie Woeste

IPC分类号： G06F13/36

CPC分类号： G06F13/4204 ,  Y02D10/14 ,  Y02D10/151

摘要： A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

摘要翻译： 高速计算机处理器系统包括用于图形处理器的高速接口。 在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

公开(公告)号：US07359432B2

公开(公告)日：2008-04-15

申请号：US11622527

申请日：2007-01-12

申请人： Steven John Baumgartner

发明人： Steven John Baumgartner

IPC分类号： H04B1/38 ,  H04L27/08

CPC分类号： H04L1/0002 ,  H04B1/38 ,  H04B10/40 ,  H04L5/1446

摘要： An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.

摘要翻译： 实现了具有不同操作速度特性的收发器之间的自动波特率速度协商的布置。 当发生指示可能的波特率不匹配的事件时，产生控制信号并用于触发波特率协商过程。 在波特率协商过程中，发送预定模式，解码各发送收发器的波特率，解码波特率用于选择收发器的适当滤波。