利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.017 秒)

    Auxiliary ROM memory system
    6.
    发明授权
    Auxiliary ROM memory system 失效
    辅助ROM存储系统

    公开(公告)号：US4141068A

    公开(公告)日：1979-02-20

    申请号：US780875

    申请日：1977-03-24

    申请人： George E. Mager ,  Frank M. Nelson ,  Steven L. Reid ,  Philip Richardson ,  Vernon E. Rochat ,  Donald S. Post

    发明人： George E. Mager ,  Frank M. Nelson ,  Steven L. Reid ,  Philip Richardson ,  Vernon E. Rochat ,  Donald S. Post

    IPC分类号： G06F12/06 ,  G06F9/26 ,  G06F9/445 ,  G06F13/00

    CPC分类号： G06F8/66 ,  G06F12/0638

    摘要： An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

    摘要翻译： 分级的辅助ROM存储器系统，用于提供附加的只读存储器控制程序存储要求的过多或替代提供在基于微处理器的中央处理单元模块上的预定ROM存储器的可能性，以及只读 利用可编程只读存储器来加快对ROM位模式的改变的实现/安装的存​​储器改变能力。 可变的PROM存储器包括批量PROM存储器，其包括与现有的板上ROM存储器相互排斥的第一PROM集合，用于可寻址地分支到代码扩展和/或在线代码插入，和/或相互间的第二PROM集合 包括存在的板载和即时ROM存储器，用于可解码地寻址大规模代码覆盖。 另外，可改变的PROM存储器包括补丁PROM，用于通过多级解码将小规模代码叠加到板上以及用于单列直插位模式改变的偶然ROM存储器中。 涉及存储器请求的相互关联的存储器请求被提供给存储器优先级的预定层级以进行解析，这些存储器请求涉及由超过一个存储器类别识别的地址的存储器请求。 辅助ROM存储器系统的每个枚举的存储器类别可以操作以使其总体增加或减少，而不使上述寻址层次化。

    System and method for reducing oscillating tool-induced reaction forces
    8.
    发明授权
    System and method for reducing oscillating tool-induced reaction forces 有权

    公开(公告)号：US06621241B2

    公开(公告)日：2003-09-16

    申请号：US10028501

    申请日：2001-12-20

    申请人： Steven L. Reid ,  John R. Keller ,  Joseph K. Bond

    发明人： Steven L. Reid ,  John R. Keller ,  Joseph K. Bond

    IPC分类号： H02K3300

    CPC分类号： F16F15/02 ,  G05B5/01

    摘要： A system and method for reducing reaction forces induced in a machine frame by an oscillating tool employs a counterforce assembly which is driven to move along linear slides mounted to the machine frame. The counterforce assembly is driven with a drive signal derived from two signals: a first signal which is proportional to the acceleration of the tool, and a second signal which is directly proportional to the velocity of the oscillating tool. By properly-adjusting the acceleration and velocity components of the drive signal, the magnitude of the reaction forces induced in the machine frame by the oscillating tool can be substantially reduced. The counterforce assembly preferably includes a centering means which prevents it from moving to either end of the slide. An accelerometer is preferably mounted to the machine frame to sense its vibration, with the accelerometer output used to adjust the counterforce assembly's drive electronics to reduce vibration to a minimum.