公开(公告)号：US07518941B2

公开(公告)日：2009-04-14

申请号：US11512676

申请日：2006-08-30

申请人： Steven Richard Jahnke ,  Hiromichi Hamakawa

发明人： Steven Richard Jahnke ,  Hiromichi Hamakawa

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C11/413

摘要： Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.

摘要翻译： 公开了为存储器件的局部超范围读取请求提供刷新的方法和装置。 这里公开的示例性方法向存储器单元提供读取信号。 在从最高有效位行地址线到最低有效位行地址线的行地址线上接收地址。 固定的高逻辑输入耦合到与本地超出范围地址相关联的行驱动器逻辑器件的第一输入。 如果地址是本地超出范围地址，则提供逻辑以在耦合到耦合到存储器单元的行驱动器逻辑器件的输出的位线上发送读使能信号。

公开(公告)号：US20080056054A1

公开(公告)日：2008-03-06

申请号：US11512676

申请日：2006-08-30

申请人： Steven Richard Jahnke ,  Hiromichi Hamakawa

发明人： Steven Richard Jahnke ,  Hiromichi Hamakawa

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C11/413

摘要： Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.

摘要翻译： 公开了为存储器件的局部超范围读取请求提供刷新的方法和装置。 这里公开的示例性方法向存储器单元提供读取信号。 在从最高有效位行地址线到最低有效位行地址线的行地址线上接收地址。 固定的高逻辑输入耦合到与本地超出范围地址相关联的行驱动器逻辑器件的第一输入。 如果地址是本地超出范围地址，则提供逻辑以在耦合到耦合到存储器单元的行驱动器逻辑器件的输出的位线上发送读使能信号。

公开(公告)号：US08589650B2

公开(公告)日：2013-11-19

申请号：US12815891

申请日：2010-06-15

申请人： Satoshi Yokoya ,  Philippe Gentric ,  Alain Michel Breton ,  Steven Charles Goss ,  Steven Richard Jahnke

发明人： Satoshi Yokoya ,  Philippe Gentric ,  Alain Michel Breton ,  Steven Charles Goss ,  Steven Richard Jahnke

IPC分类号： G06F12/02

CPC分类号： G06F1/3275 ,  G06F12/023 ,  G06F12/06 ,  G06F12/08 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

摘要： In a digital system with a processor coupled to a paged memory system, the memory system may be dynamically configured using a memory compaction manager in order to allow portions of the memory to be placed in a low power mode. As applications are executed by the processor, program instructions are copied from a non-volatile memory coupled to the processor into pages of the paged memory system under control of an operating system. Pages in the paged memory system that are not being used by the processor are periodically identified. The paged memory system is compacted by copying pages that are being used by the processor from a second region of the paged memory into a first region of the paged memory. The second region may be placed in a low power mode when it contains no pages that are being used by the processor.

摘要翻译： 在具有耦合到分页存储器系统的处理器的数字系统中，可以使用存储器压缩管理器动态地配置存储器系统，以便允许存储器的部分被置于低功率模式。 当处理器执行应用时，在操作系统的控制下，将程序指令从耦合到处理器的非易失性存储器复制到寻呼存储器系统的页面。 周期性地识别分页存储器系统中未被处理器使用的页面。 通过将处理器使用的页面从分页存储器的第二区域复制到分页存储器的第一区域来压缩分页存储器系统。 当第二区域不包含处理器正在使用的页面时，第二区域可以被置于低功率模式。

公开(公告)号：US20110283071A1

公开(公告)日：2011-11-17

申请号：US12815891

申请日：2010-06-15

申请人： Satoshi Yokoya ,  Philippe Gentric ,  Alain Michel Breton ,  Steven Charles Goss ,  Steven Richard Jahnke

发明人： Satoshi Yokoya ,  Philippe Gentric ,  Alain Michel Breton ,  Steven Charles Goss ,  Steven Richard Jahnke

IPC分类号： G06F12/00 ,  G06F1/32 ,  G06F12/16

CPC分类号： G06F1/3275 ,  G06F12/023 ,  G06F12/06 ,  G06F12/08 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

摘要： In a digital system with a processor coupled to a paged memory system, the memory system may be dynamically configured using a memory compaction manager in order to allow portions of the memory to be placed in a low power mode. As applications are executed by the processor, program instructions are copied from a non-volatile memory coupled to the processor into pages of the paged memory system under control of an operating system. Pages in the paged memory system that are not being used by the processor are periodically identified. The paged memory system is compacted by copying pages that are being used by the processor from a second region of the paged memory into a first region of the paged memory. The second region may be placed in a low power mode when it contains no pages that are being used by the processor.

摘要翻译： 在具有耦合到分页存储器系统的处理器的数字系统中，可以使用存储器压缩管理器动态地配置存储器系统，以便允许存储器的部分被置于低功率模式。 当处理器执行应用时，在操作系统的控制下，将程序指令从耦合到处理器的非易失性存储器复制到寻呼存储器系统的页面。 周期性地识别分页存储器系统中未被处理器使用的页面。 通过将处理器使用的页面从分页存储器的第二区域复制到分页存储器的第一区域来压缩分页存储器系统。 当第二区域不包含处理器正在使用的页面时，第二区域可以被置于低功率模式。