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公开(公告)号:US07746969B2
公开(公告)日:2010-06-29
申请号:US11391903
申请日:2006-03-28
申请人: Thomas Bryan , Stewart Webb , Peter Sallaway , Tulsi Manickam , Sreen Raghavan
发明人: Thomas Bryan , Stewart Webb , Peter Sallaway , Tulsi Manickam , Sreen Raghavan
IPC分类号: H04B1/10
CPC分类号: H04L25/03057 , H04L7/0062 , H04L7/0334 , H04L25/03878
摘要: A receiver for a multi-channel system such as a HDMI system is presented. In accordance with the present invention, the receiver receives one of the plurality of channels and includes an analog portion, a digital-to-analog converter, and a digital control block that provides digital control signals to the analog portion. Equalization can be accomplished partially or wholly in the analog domain and digitally controlled by a digital control loop. A digital equalizer can also be included. A decision feedback equalizer can be implemented that sums an analog output signal into the analog data stream. Timing recovery can be accomplished by digital control of a phase interpolator or delay locked loop that receives a plurality of phases from a timing circuit coupled to receive a clock signal.
摘要翻译: 提出了用于诸如HDMI系统的多通道系统的接收器。 根据本发明,接收机接收多个信道中的一个,并且包括模拟部分,数模转换器和向模拟部分提供数字控制信号的数字控制块。 均衡可以部分或全部在模拟域中完成,并由数字控制回路数字控制。 也可以包括数字均衡器。 可以实现将模拟输出信号和模拟数据流相加的判决反馈均衡器。 可以通过数字控制相位内插器或延迟锁定环来实现定时恢复,该锁相环从耦合到接收时钟信号的定时电路接收多个相位。
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公开(公告)号:US20070230640A1
公开(公告)日:2007-10-04
申请号:US11391903
申请日:2006-03-28
申请人: Thomas Bryan , Stewart Webb , Peter Sallaway , Tulsi Manickam , Sreen Raghavan
发明人: Thomas Bryan , Stewart Webb , Peter Sallaway , Tulsi Manickam , Sreen Raghavan
CPC分类号: H04L25/03057 , H04L7/0062 , H04L7/0334 , H04L25/03878
摘要: A receiver for a multi-channel system such as a HDMI system is presented. In accordance with the present invention, the receiver receives one of the plurality of channels and includes an analog portion, a digital-to-analog converter, and a digital control block that provides digital control signals to the analog portion. Equalization can be accomplished partially or wholly in the analog domain and digitally controlled by a digital control loop. A digital equalizer can also be included. A decision feedback equalizer can be implemented that sums an analog output signal into the analog data stream. Timing recovery can be accomplished by digital control of a phase interpolator or delay locked loop that receives a plurality of phases from a timing circuit coupled to receive a clock signal.
摘要翻译: 提出了用于诸如HDMI系统的多通道系统的接收器。 根据本发明,接收机接收多个信道中的一个,并且包括模拟部分,数模转换器和向模拟部分提供数字控制信号的数字控制块。 均衡可以部分或全部在模拟域中完成,并由数字控制回路数字控制。 也可以包括数字均衡器。 可以实现将模拟输出信号和模拟数据流相加的判决反馈均衡器。 可以通过数字控制相位内插器或延迟锁定环来实现定时恢复,该锁相环从耦合到接收时钟信号的定时电路接收多个相位。
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公开(公告)号:US2455840A
公开(公告)日:1948-12-07
申请号:US56171044
申请日:1944-11-03
申请人: STEWART WEBB JAMES
发明人: STEWART WEBB JAMES
IPC分类号: B27B5/10
CPC分类号: B27B5/10 , Y10S83/928
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