公开(公告)号：US20090051014A1

公开(公告)日：2009-02-26

申请号：US12285851

申请日：2008-10-15

申请人： Ki-seog Youn ,  Jong-hyon Ahn ,  Su-gon Bae

发明人： Ki-seog Youn ,  Jong-hyon Ahn ,  Su-gon Bae

IPC分类号： H01L29/06

CPC分类号： H01L21/823443 ,  H01L21/823418

摘要： A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.

摘要翻译： 提供一种制造具有硅化物层的半导体器件的方法和通过该方法制造的半导体器件。 该方法可以包括提供具有有源区和场区的半导体衬底，并且在有源区和场区中的每一个上形成多个栅极图案。 多个栅极图案可以各自具有侧壁间隔物。 场区域上的多个栅极图案包括至少两个相邻的栅极图案。 该方法可以包括形成硅化物阻挡层图案，其掩蔽存在于场区域上的每个相邻栅极图案之间的场区域的一部分。 该方法还可以包括在有源区上形成硅化物层以及未被硅化物阻挡层图案掩蔽的多个栅极图案中的任何一个。

公开(公告)号：US07709340B2

公开(公告)日：2010-05-04

申请号：US11705164

申请日：2007-02-12

申请人： Jong-hyon Ahn ,  Jae-cheol Yoo ,  Ki-seog Youn ,  Kwan-jong Roh ,  Su-gon Bae ,  Ki-young Kim

发明人： Jong-hyon Ahn ,  Jae-cheol Yoo ,  Ki-seog Youn ,  Kwan-jong Roh ,  Su-gon Bae ,  Ki-young Kim

IPC分类号： H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

摘要： A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.

摘要翻译： 半导体集成电路器件可以包括半导体衬底，半导体衬底上的静态存储单元，下拉晶体管上的拉伸应力膜以及通过晶体管上的压应力膜。 静态存储单元可以包括形成锁存器的多个上拉晶体管和下拉晶体管，并且多通道晶体管可用于访问锁存器。

公开(公告)号：US20050170575A1

公开(公告)日：2005-08-04

申请号：US11034865

申请日：2005-01-14

申请人： Hyae-ryoung Lee ,  Su-gon Bae

发明人： Hyae-ryoung Lee ,  Su-gon Bae

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823857

摘要： A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.

摘要翻译： 制造半导体器件的双栅极氧化物的方法包括在衬底的整个表面上形成第一栅极绝缘层，去除第一栅极绝缘层的一部分以使用第一掩模选择性地暴露衬底的第一区域;以及 使用所述第一掩模对所述衬底的所述选择性曝光的第一区域进行离子注入，以及在所述第一栅极绝缘层和所述衬底的暴露的第一区域上形成第二栅极绝缘层，以形成具有第一厚度 在衬底的第一区域上方，并且在衬底的剩余区域上具有第二厚度，第一厚度和第二厚度不同。

公开(公告)号：US07534677B2

公开(公告)日：2009-05-19

申请号：US11034865

申请日：2005-01-14

申请人： Hyae-ryoung Lee ,  Su-gon Bae

发明人： Hyae-ryoung Lee ,  Su-gon Bae

IPC分类号： H01L21/84

CPC分类号： H01L21/823857

摘要： A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.

摘要翻译： 制造半导体器件的双栅极氧化物的方法包括在衬底的整个表面上形成第一栅极绝缘层，去除第一栅极绝缘层的一部分以使用第一掩模选择性地暴露衬底的第一区域;以及 使用所述第一掩模对所述衬底的所述选择性曝光的第一区域进行离子注入，以及在所述第一栅极绝缘层和所述衬底的暴露的第一区域上形成第二栅极绝缘层，以形成具有第一厚度 在衬底的第一区域上方，并且在衬底的剩余区域上具有第二厚度，第一厚度和第二厚度不同。

公开(公告)号：US20070187770A1

公开(公告)日：2007-08-16

申请号：US11705164

申请日：2007-02-12

申请人： Jong-hyon Ahn ,  Jae-cheol Yoo ,  Ki-seog Youn ,  Kwan-jong Roh ,  Su-gon Bae ,  Ki-young Kim

发明人： Jong-hyon Ahn ,  Jae-cheol Yoo ,  Ki-seog Youn ,  Kwan-jong Roh ,  Su-gon Bae ,  Ki-young Kim

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

摘要： A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.

摘要翻译： 半导体集成电路器件可以包括半导体衬底，半导体衬底上的静态存储单元，下拉晶体管上的拉伸应力膜以及通过晶体管上的压应力膜。 静态存储单元可以包括形成锁存器的多个上拉晶体管和下拉晶体管，并且多通道晶体管可用于访问锁存器。

公开(公告)号：US20060163669A1

公开(公告)日：2006-07-27

申请号：US11332150

申请日：2006-01-17

申请人： Ki-seog Youn ,  Jong-hyon Ahn ,  Su-gon Bae

发明人： Ki-seog Youn ,  Jong-hyon Ahn ,  Su-gon Bae

IPC分类号： H01L29/76

CPC分类号： H01L21/823443 ,  H01L21/823418

摘要： A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.