公开(公告)号：US20060072257A1

公开(公告)日：2006-04-06

申请号：US10954672

申请日：2004-09-30

Applicant: Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

Inventor： Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

IPC: H02H9/00

CPC classification number: H01L23/528 ,  H01L21/7684 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An critical interconnect line (300) for an integrated circuit is provided in which the problem of dishing of copper is addressed. An interconnect line (300) is provided for an integrated circuit in the form of a critical interconnect line modelled as a transmission line. The interconnect line (300) is formed of a conductive material having a width (302) and a length (303). The interconnect line (300) comprises at least two fingers (304, 305, 306) extending the length (303) of the interconnect line (300), an elongate aperture (309) in the conductive material separating two adjacent fingers (304, 305, 306), and one or more bridges (308) joining the fingers (304, 305, 306) at intervals along the length (303) of the interconnect line (300). The fingers (303, 304, 305) are kept within a width for which the effect of dishing acceptable width whilst the bridges (307, 308) keep the fingers (304, 305, 306) at the same potential difference.

Abstract translation: 提供了一种用于集成电路的关键互连线（300），其中解决了铜的凹陷问题。 为以建模为传输线的关键互连线的形式的集成电路提供互连线（300）。 互连线（300）由具有宽度（302）和长度（303）的导电材料形成。 互连线（300）包括延伸互连线（300）的长度（303）的至少两个指状物（304,305,306），导电材料中的细长孔（309），分隔两个相邻的指状物（304,305 ，306）和沿着所述互连线（300）的长度（303）的间隔连接所述指状物（304,305,306）的一个或多个桥接器（308）。 手指（303,304,305）保持在一个宽度内，当桥接器（307,308）将手指（304,305,306）保持在相同的电位差时，凹槽可接受宽度的影响。

公开(公告)号：US20050102644A1

公开(公告)日：2005-05-12

申请号：US10605960

申请日：2003-11-10

Applicant: David Collins ,  Donald Jordan ,  Sue Strang ,  Steven Voldman

Inventor： David Collins ,  Donald Jordan ,  Sue Strang ,  Steven Voldman

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5036

Abstract: A computerized method and system for designing, verification and checking of the electrostatic discharge (ESD) protection circuits and their implementation in a integrated computer chip design where the computer chip comprises of electronic circuits designed in a parameterized cell design system, pads, interconnects and the ESD system uses a hierarchical system of parameterized cells (p-cells) which are constructed into higher level ESD networks. Lowest order p-cells pass user defined parameters to higher order p-cells to form an ESD protection circuit meeting design criteria. Ones of the p-cells are “grow-able” such that they can form repetition groups of the underlying p-cell element to accommodate the design parameters. Layout and circuit schematics are auto-generated with the user varying the number of elements in the circuit by adjusting the input parameters. The circuit topology automation allows for the customer to auto generate new ESD circuits and ESD power clamps without additional design work.

Abstract translation: 一种用于设计，验证和检查静电放电（ESD）保护电路的计算机化方法和系统及其在集成计算机芯片设计中的实现，其中计算机芯片包括在参数化单元设计系统，焊盘，互连和 ESD系统使用构建到更高级别ESD网络中的参数化单元（p-cell）的分层系统。 最低阶p单元将用户定义的参数传递到高阶p单元，以形成符合设计标准的ESD保护电路。 p细胞的一部分是“可生长的”，使得它们可以形成下面的p细胞元件的重复组以适应设计参数。 布局和电路原理图是通过用户通过调整输入参数来改变电路中的元件数量而自动生成的。 电路拓扑自动化允许客户自动生成新的ESD电路和ESD电源夹，而无需额外的设计工作。