公开(公告)号：US20160247728A1

公开(公告)日：2016-08-25

申请号：US14981267

申请日：2015-12-28

申请人： Junggun YOU ,  Sukhoon JEONG

发明人： Junggun YOU ,  Sukhoon JEONG

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

摘要翻译： 制造半导体器件的方法包括在半导体衬底中形成第一阱区域和第二阱区域，在半导体衬底上形成限定第一鳍片有源区域和第二鳍片有源区域的隔离区域，形成牺牲栅极层 所述半导体衬底具有所述第一和第二鳍片活动区域和所述隔离区域，在所述牺牲栅极层上形成硬掩模线，形成在所述硬掩模线上具有栅极切割开口的栅极截止掩模，以及形成间隔开的第一和第二硬掩模图案 通过使用栅极切割掩模来蚀刻硬掩模线作为蚀刻掩模。 栅极切割开口与形成在第一和第二鳍状物活性区域之间的第一和第二阱区域之间的边界重叠，并且在与硬掩模线相交的方向上具有线状。

公开(公告)号：US10199279B2

公开(公告)日：2019-02-05

申请号：US15793491

申请日：2017-10-25

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US20180047636A1

公开(公告)日：2018-02-15

申请号：US15793491

申请日：2017-10-25

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US09842778B2

公开(公告)日：2017-12-12

申请号：US14981267

申请日：2015-12-28

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.