公开(公告)号：US10199279B2

公开(公告)日：2019-02-05

申请号：US15793491

申请日：2017-10-25

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US20180047636A1

公开(公告)日：2018-02-15

申请号：US15793491

申请日：2017-10-25

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US09842778B2

公开(公告)日：2017-12-12

申请号：US14981267

申请日：2015-12-28

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US09640659B2

公开(公告)日：2017-05-02

申请号：US15050784

申请日：2016-02-23

申请人： Junggun You ,  Jeongmin Choi ,  Ingyum Kim

发明人： Junggun You ,  Jeongmin Choi ,  Ingyum Kim

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/6681

摘要： Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width.

公开(公告)号：US09704865B2

公开(公告)日：2017-07-11

申请号：US14969319

申请日：2015-12-15

申请人： Hyungjong Lee ,  Wei-Hua Hsu ,  Junggun You ,  Choongho Lee

发明人： Hyungjong Lee ,  Wei-Hua Hsu ,  Junggun You ,  Choongho Lee

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area.