公开(公告)号：US20160284680A1

公开(公告)日：2016-09-29

申请号：US15050607

申请日：2016-02-23

申请人： Changseop YOON ,  Junggun YOU ,  YoungJoon PARK ,  Jeonghyo LEE

发明人： Changseop YOON ,  Junggun YOU ,  YoungJoon PARK ,  Jeonghyo LEE

IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L29/423 ,  H01L27/108 ,  H01L29/06

CPC分类号： H01L29/7846 ,  H01L21/76224 ,  H01L27/11807 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659

摘要： A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.

摘要翻译： 半导体器件包括：第一器件隔离层，其限定沿着衬底上的第一方向彼此间隔开的有源区，第二器件隔离层限定从衬底突出的多个有源图案，第二器件隔离层沿第一方向延伸 在第二方向上彼此间隔开并连接到第一器件隔离层，栅极结构在第一器件隔离层上的第二方向上延伸在有源区之间，第二器件隔离层的顶表面较低 比活性图案的顶表面，第一器件隔离层的顶表面高于有源图案的顶表面，并且栅极结构的底表面的至少一部分高于活性图案的顶表面 模式。

公开(公告)号：US20160247728A1

公开(公告)日：2016-08-25

申请号：US14981267

申请日：2015-12-28

申请人： Junggun YOU ,  Sukhoon JEONG

发明人： Junggun YOU ,  Sukhoon JEONG

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

摘要翻译： 制造半导体器件的方法包括在半导体衬底中形成第一阱区域和第二阱区域，在半导体衬底上形成限定第一鳍片有源区域和第二鳍片有源区域的隔离区域，形成牺牲栅极层 所述半导体衬底具有所述第一和第二鳍片活动区域和所述隔离区域，在所述牺牲栅极层上形成硬掩模线，形成在所述硬掩模线上具有栅极切割开口的栅极截止掩模，以及形成间隔开的第一和第二硬掩模图案 通过使用栅极切割掩模来蚀刻硬掩模线作为蚀刻掩模。 栅极切割开口与形成在第一和第二鳍状物活性区域之间的第一和第二阱区域之间的边界重叠，并且在与硬掩模线相交的方向上具有线状。

公开(公告)号：US20160197074A1

公开(公告)日：2016-07-07

申请号：US14969319

申请日：2015-12-15

申请人： Hyungjong LEE ,  Wei-Hua HSU ,  Junggun YOU ,  Choongho LEE

发明人： Hyungjong LEE ,  Wei-Hua HSU ,  Junggun YOU ,  Choongho LEE

IPC分类号： H01L27/092 ,  H01L23/532 ,  H01L23/535 ,  H01L29/423

CPC分类号： H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area.

摘要翻译： 具有双重硅化物的半导体器件在衬底上包括具有N型杂质的第一鳍片和具有P型杂质的第二鳍片。 第一栅极电极和第一源极/漏极区域在第一鳍片上。 第二栅极电极和第二源极/漏极区域在第二鳍片上。 蚀刻停止层位于第一源极/漏极区域和第二源极/漏极区域上。 绝缘层位于蚀刻停止层上。 连接到第一源极/漏极区域的第一插头和连接到第二源极/漏极区域的第二插头穿过绝缘层和蚀刻停止层。 第一金属硅化物层位于第一源极/漏极区域中。 具有不同于第一金属硅化物层并且具有小于第一金属硅化物层的厚度的材料的第二金属硅化物层位于第二源极/漏极区域中。

公开(公告)号：US10199279B2

公开(公告)日：2019-02-05

申请号：US15793491

申请日：2017-10-25

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US09640659B2

公开(公告)日：2017-05-02

申请号：US15050784

申请日：2016-02-23

申请人： Junggun You ,  Jeongmin Choi ,  Ingyum Kim

发明人： Junggun You ,  Jeongmin Choi ,  Ingyum Kim

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/6681

摘要： Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width.

公开(公告)号：US20160247730A1

公开(公告)日：2016-08-25

申请号：US15050784

申请日：2016-02-23

申请人： Junggun YOU ,  Jeongmin Choi ,  Ingyum Kim

发明人： Junggun YOU ,  Jeongmin Choi ,  Ingyum Kim

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/6681

摘要： Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width.

摘要翻译： 制造半导体器件的方法可以包括在半导体衬底上形成限定多个鳍状有源区的隔离区，在半导体衬底上形成牺牲栅极层，形成穿过第一和第二鳍状活性区的第一硬掩模线和 并且形成具有多个栅极切割开口的栅极切割掩模。 多个栅极切割开口可以包括分别具有第一宽度并且与第一和第二鳍片活动区域相邻的第一和第二栅极切割开口以及与边缘鳍片活动区域相邻的边缘栅极切割开口，并且具有 第二宽度大于第一宽度但小于第一宽度尺寸的两倍。

公开(公告)号：US20180047636A1

公开(公告)日：2018-02-15

申请号：US15793491

申请日：2017-10-25

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US09842778B2

公开(公告)日：2017-12-12

申请号：US14981267

申请日：2015-12-28

申请人： Junggun You ,  Sukhoon Jeong

发明人： Junggun You ,  Sukhoon Jeong

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.

公开(公告)号：US09704865B2

公开(公告)日：2017-07-11

申请号：US14969319

申请日：2015-12-15

申请人： Hyungjong Lee ,  Wei-Hua Hsu ,  Junggun You ,  Choongho Lee

发明人： Hyungjong Lee ,  Wei-Hua Hsu ,  Junggun You ,  Choongho Lee

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/665 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area.