公开(公告)号：US07863152B2

公开(公告)日：2011-01-04

申请号：US12072445

申请日：2008-02-26

申请人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  Quan WangXiao ,  Hyun-min Choi

发明人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  Quan WangXiao ,  Hyun-min Choi

IPC分类号： H01L21/762

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

摘要翻译： 提供了具有应变层的半导体器件和制造具有能够减小负载效应的应变层的半导体器件的方法。 通过设置不重叠的活动假人和门虚拟物，可以确保将形成应变层虚拟物的活动虚拟物的面积，从而降低装载效果。

公开(公告)号：US20080211059A1

公开(公告)日：2008-09-04

申请号：US12013290

申请日：2008-01-11

申请人： Dae-Jin KWON ,  Woo-Sik KIM ,  Maeda Shigenobu ,  Seung-Hwan LEE ,  Sung-Rey WI ,  Wang-Xiao Quan ,  Hyun-Min CHOI

发明人： Dae-Jin KWON ,  Woo-Sik KIM ,  Maeda Shigenobu ,  Seung-Hwan LEE ,  Sung-Rey WI ,  Wang-Xiao Quan ,  Hyun-Min CHOI

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line to prevent a rupture of the electrical fuse such that heat, which is generated in the fuse line during a blowing of the fuse line, is spread throughout the heat spreading structure. Thus, a sensing margin of the electrical fuse can be secured and a deterioration of devices adjacent to the electrical fuse by heat generated in the electrical fuse can be prevented.

摘要翻译： 半导体器件包括用于熔丝编程的熔丝晶体管和连接到熔丝晶体管的熔丝块，其中熔丝块包括熔丝线和连接到熔丝线的散热结构。 电熔丝采用连接到熔丝线的散热结构，以防止电熔丝断裂，使得在熔断丝熔化期间在熔丝线中产生的热量散布在整个散热结构中。 因此，可以确保电熔丝的感测余量，并且可以防止在电熔丝中产生的热量与电熔丝相邻的器件的劣化。

公开(公告)号：US07888772B2

公开(公告)日：2011-02-15

申请号：US12013290

申请日：2008-01-11

申请人： Dae-Jin Kwon ,  Woo-Sik Kim ,  Maeda Shigenobu ,  Seung-Hwan Lee ,  Sung-Rey Wi ,  Wang-Xiao Quan ,  Hyun-Min Choi

发明人： Dae-Jin Kwon ,  Woo-Sik Kim ,  Maeda Shigenobu ,  Seung-Hwan Lee ,  Sung-Rey Wi ,  Wang-Xiao Quan ,  Hyun-Min Choi

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line to prevent a rupture of the electrical fuse such that heat, which is generated in the fuse line during a blowing of the fuse line, is spread throughout the heat spreading structure. Thus, a sensing margin of the electrical fuse can be secured and a deterioration of devices adjacent to the electrical fuse by heat generated in the electrical fuse can be prevented.

摘要翻译： 半导体器件包括用于熔丝编程的熔丝晶体管和连接到熔丝晶体管的熔丝块，其中熔丝块包括熔丝线和连接到熔丝线的散热结构。 电熔丝采用连接到熔丝线的散热结构，以防止电熔丝断裂，使得在熔断丝熔化期间在熔丝线中产生的热量散布在整个散热结构中。 因此，可以确保电熔丝的感测余量，并且可以防止在电熔丝中产生的热量与电熔丝相邻的器件的劣化。

公开(公告)号：US20080246092A1

公开(公告)日：2008-10-09

申请号：US12072445

申请日：2008-02-26

申请人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-Min Choi

发明人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-Min Choi

IPC分类号： H01L29/00 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

摘要翻译： 提供了具有应变层的半导体器件和制造具有能够减小负载效应的应变层的半导体器件的方法。 通过设置不重叠的活动假人和门虚拟物，可以确保将形成应变层虚拟物的活动虚拟物的面积，从而降低装载效果。

公开(公告)号：US08350354B2

公开(公告)日：2013-01-08

申请号：US12951808

申请日：2010-11-22

申请人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-min Choi

发明人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-min Choi

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

摘要翻译： 提供了具有应变层的半导体器件和制造具有能够减小负载效应的应变层的半导体器件的方法。 通过设置不重叠的活动假人和门虚拟物，可以确保将形成应变层虚拟物的活动虚拟物的面积，从而降低装载效果。

公开(公告)号：US20110062497A1

公开(公告)日：2011-03-17

申请号：US12951808

申请日：2010-11-22

申请人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  Quan WangXiao ,  Hyun-min Choi

发明人： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  Quan WangXiao ,  Hyun-min Choi

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

摘要翻译： 提供了具有应变层的半导体器件和制造具有能够减小负载效应的应变层的半导体器件的方法。 通过设置不重叠的活动假人和门虚拟物，可以确保将形成应变层虚拟物的活动虚拟物的面积，从而降低装载效果。