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    MTCMOS flip-flop circuit capable of retaining data in sleep mode
    1.
    发明授权
    MTCMOS flip-flop circuit capable of retaining data in sleep mode 有权
    MTCMOS触发器电路能够将数据保存在睡眠模式

    公开(公告)号：US06870412B2

    公开(公告)日：2005-03-22

    申请号：US10674847

    申请日：2003-09-29

    Applicant: Sung-We Cho

    Inventor： Sung-We Cho

    IPC: H03K3/3562 ,  H03K3/037 ,  H03K3/356 ,  H03K3/289 ,  H03K3/359

    CPC classification number: H03K3/356008

    Abstract: The present invention relates to a flip-flop circuit employing an MTCMOS technology comprising a master latch unit and a slave latch unit, for latching input data and outputting the data under the control of an internal clock signal, wherein an output of the flip-flop circuit retains a state just before the admission to sleep mode when the state of the system is converted from sleep mode to active by means of making a data state of an input terminal of a master latch into the same state as an inversed data state of an input terminal of a slave latch circuit in sleep mode and storing it. The flip-flop circuit employing the MTCMOS technology in accordance with the present invention is capable of retaining a state just before the sleep mode when the state of the system is converted from sleep mode to active mode by using the sleep mode control signal by means of adding the feedback circuit to the conventional flip-flop circuit. In addition, while the flip-flop circuit employing the MTCMOS technology in accordance with the present invention has an operation speed slightly slower than that of the prior art flip-flop circuit employing the low-Vth transistor or the high-Vth transistor, a leakage current of the present invention is significantly smaller than that of the conventional art.

    Abstract translation: 本发明涉及采用包括主锁存单元和从锁存单元的MTCMOS技术的触发器电路，用于锁存输入数据并在内部时钟信号的控制下输出数据，其中触发器的输出 当系统状态从睡眠模式转换为活动状态时，通过使主锁存器的输入端的数据状态变成与主存储器的反相数据状态相同的状态，电路在进入睡眠模式之前保持状态。 从锁存电路的输入端子处于睡眠模式并存储。 采用根据本发明的MTCMOS技术的触发器电路能够通过使用睡眠模式控制信号通过使用睡眠模式控制信号来将系统的状态从睡眠模式转换到活动模式时保持刚好在睡眠模式之前的状态 将反馈电路添加到传统的触发器电路。 此外，虽然采用根据本发明的MTCMOS技术的触发器电路的操作速度比采用低Vth晶体管或高Vth晶体管的现有技术的触发器电路的操作速度稍慢，但是泄漏 本发明的电流明显小于常规技术。

    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    2.
    发明申请
    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 有权
    集成电路和半导体器件

    公开(公告)号：US20160300839A1

    公开(公告)日：2016-10-13

    申请号：US15093504

    申请日：2016-04-07

    Applicant: Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    Inventor： Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    IPC: H01L27/092 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

    CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

    Abstract translation: 实施例包括包括标准单元的集成电路，该标准单元包括：具有不同导电类型并沿第一方向延伸的第一和第二有源区; 第一，第二和第三导电线在基本上垂直于第一方向的第二方向上在第一和第二有源区上延伸并彼此平行设置; 以及切割层，其在所述第一和第二有源区域之间沿所述第一方向延伸，并且将所述第一导电线分离成第一上导电线和第一下导电线，所述第二导线变为第二上导电线和第二下导电线 线和第三导线插入第三上导电线和第三下导电线; 其中：所述第一上导电线和所述第三下导电线电连接在一起; 并且第二上导线和第二下导电线电连接在一起。

    Integrated circuit and semiconductor device
    5.
    发明授权
    Integrated circuit and semiconductor device 有权
    集成电路和半导体器件

    公开(公告)号：US09583493B2

    公开(公告)日：2017-02-28

    申请号：US15093504

    申请日：2016-04-07

    Applicant: Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    Inventor： Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    IPC: H01L23/52 ,  H01L27/092 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02

    CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

    Abstract translation: 实施例包括包括标准单元的集成电路，该标准单元包括：具有不同导电类型并沿第一方向延伸的第一和第二有源区; 第一，第二和第三导电线在基本上垂直于第一方向的第二方向上在第一和第二有源区上延伸并彼此平行设置; 以及切割层，其在所述第一和第二有源区域之间沿所述第一方向延伸，并且将所述第一导电线分离成第一上导电线和第一下导电线，所述第二导线变为第二上导电线和第二下导电线 线和第三导线插入第三上导电线和第三下导电线; 其中：所述第一上导电线和所述第三下导电线电连接在一起; 并且第二上导线和第二下导电线电连接在一起。

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