公开(公告)号：US20050032277A1

公开(公告)日：2005-02-10

申请号：US10937424

申请日：2004-09-07

Applicant: Richard Ferrant ,  T. C. Chan

Inventor： Richard Ferrant ,  T. C. Chan

IPC: H01L27/11 ,  G11C11/412 ,  H01L21/8244 ,  H01L29/76 ,  H01L21/82

CPC classification number: G11C11/412

Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair. The threshold voltage of the first and second pass gate transistors is such that a subthreshold current is provided to the first and second pull-down transistors when the memory cell is not being accessed such that the conduction terminal of the pull-down transistor that is turned off is maintained at a voltage level corresponding to a logic high voltage. In this way, the memory cell is capable of performing a latching function without pull-up transistors.

Abstract translation: 公开了一种随机存取存储单元及其制造方法。 随机存取存储单元包括交叉耦合的第一和第二下拉晶体管，使得第一下拉晶体管的控制端子连接到第二下拉晶体管的导通端子，并且控制端子 第二下拉晶体管连接到第一下拉晶体管的导通端子。 第一栅极晶体管耦合在第一晶体管的导通端和位线对的第一位线之间，第二栅极晶体管耦合在第二晶体管的导通端和位的第二位线之间 线对。 第一和第二栅极晶体管的阈值电压使得当存储单元未被访问时，向第一和第二下拉晶体管提供亚阈值电流，使得转换的下拉晶体管的导通端 关闭保持在对应于逻辑高电压的电压电平。 以这种方式，存储单元能够执行没有上拉晶体管的锁存功能。