公开(公告)号：US3924109A

公开(公告)日：1975-12-02

申请号：US49067274

申请日：1974-07-22

Applicant: TECHNOLOGY MARKETING INC

Inventor： JHU JAI HUN ,  WELLS GEORGE H ,  MULDER THOMAS J ,  MCDONALD DON E

IPC: G01R31/319 ,  G05B23/00 ,  H03K5/18

CPC classification number: G01R31/31908

Abstract: A system for testing circuits, and particularly adapted for testing printed circuit board assemblies including digital logic circuits, said circuits having multiple pin connectors, including a removable portable data storage element which defines, in machine readable form, a sequence of input signals, and additionally defines selected ones of said multiple pin connectors for application of said input signals, said storage element additionally defining, in machine readable form, the proper sequence of output signals to be produced by said circuit in response to the input signals, and selected ones of said multiple pin connectors on which said output signals should occur, and means for comparing said proper sequence of output signals with the actual output signal sequence from said circuit.

Abstract translation: 一种用于测试电路的系统，特别适用于测试包括数字逻辑电路的印刷电路板组件，所述电路具有多个引脚连接器，包括以机器可读形式定义输入信号序列的可拆卸便携式数据存储元件， 定义所述多个引脚连接器中的所选择的一个用于施加所述输入信号，所述存储元件另外以机器可读形式定义响应于所述输入信号由所述电路产生的正确的输出信号序列，以及所选择的所述输入信号 应在其上发生所述输出信号的多针连接器，以及用于将所述正确输出信号序列与来自所述电路的实际输出信号序列进行比较的装置。

公开(公告)号：US3697966A

公开(公告)日：1972-10-10

申请号：US3697966D

申请日：1971-03-25

Applicant: TECHNOLOGY MARKETING INC

Inventor： WELLS GEORGE H ,  PERSONS PERRY B

IPC: G11C11/06 ,  H03K17/00 ,  H03K17/041 ,  H03K17/60 ,  G11C5/02

CPC classification number: H03K17/601 ,  G11C11/06007 ,  H03K17/04113 ,  H03K2217/0036

Abstract: A system for supplying a current to a core memory stack having substantial inductance including a transformer having a selectively variable primary/secondary turns ratio. The variable turns ratio permits the current buildup time interval in the core state to be minimized while reducing the power required to drive the stack.

Abstract translation: 一种用于向具有实质电感的核心存储器堆栈提供电流的系统，包括具有选择性可变的初级/次级匝数比的变压器。 可变匝数比允许在核心状态下的当前累积时间间隔最小化，同时减少驱动堆栈所需的功率。

公开(公告)号：US3660829A

公开(公告)日：1972-05-02

申请号：US3660829D

申请日：1970-07-15

Applicant: TECHNOLOGY MARKETING INC

Inventor： WELLS GEORGE H ,  PERSONS PERRY B

IPC: G11C11/06 ,  G11C5/02

CPC classification number: G11C11/06007

Abstract: A current steering system is described in the context of a multi-plane magnetic core memory stack. The system is designed to control a given end of a set of core drive lines and includes a pair of bipolar switches for each pair of lines. Each bipolar switch includes two diode pairs, each pair being connected in series through a common unipolar switch to form two switchable unidirectional current paths for each bipolar switch. One current path from each bipolar switch is connected between respective ones of their associated pair of drive lines and a switchable current source of a given polarity. The remaining two current paths of the pair of bipolar switches are connected between the same two lines and a switchable current source of the opposite polarity. In this way both bipolar switches participate in controlling the flow of current in each of a pair of drive lines.

Abstract translation: 在多平面磁芯存储器堆叠的上下文中描述了当前的转向系统。 该系统设计用于控制一组核心驱动线路的给定端，并且包括用于每对线路的一对双极开关。 每个双极开关包括两个二极管对，每对通过公共单极开关串联连接，以形成每个双极开关的两个可切换单向电流通路。 来自每个双极开关的一条电流路径连接在它们相关联的一对驱动线路中的相应的一个以及给定极性的可切换电流源。 一对双极开关的剩余两个电流路径连接在相同的两条线路和相反极性的可切换电流源之间。 以这种方式，双极开关参与控制一对驱动线路中的每一个中的电流流动。