公开(公告)号：US3916332A

公开(公告)日：1975-10-28

申请号：US19627871

申请日：1971-11-08

Applicant: TEXAS INSTRUMENTS INC

Inventor： SPENCE HILTON W ,  STEHLIN ROBERT A

IPC: G11C11/06 ,  H03F3/72 ,  H03K5/02 ,  H03F3/08

CPC classification number: H03F3/72 ,  G11C11/06007 ,  H03K5/02

Abstract: A radiation tolerant differential buffer amplifier provides amplification to small amplitude input signals. Circuitry is provided to selectively gate portions of the input signals for reduction of noise problems. Biasing circuitry sets a constant DC bias level for the amplifier to accomplish generally constant triggering of the amplifier.

Abstract translation: 辐射耐受差分缓冲放大器为小幅度输入信号提供放大。 提供电路以选择性地选择输入信号的栅极部分，以减少噪声问题。 偏置电路为放大器设置恒定的直流偏置电平，以实现放大器的大体上恒定的触发。

公开(公告)号：US3878543A

公开(公告)日：1975-04-15

申请号：US42712773

申请日：1973-12-21

Applicant: HITACHI LTD

Inventor： YOSHIDA KAZUTOSHI

IPC: G11C11/06

CPC classification number: G11C11/06007

Abstract: A sensing circuit for use in a core memory, in which sense lines passing through magnetic cores have near-ends connected with an amplifier and with first termination resistors and far-ends connected with second termination resistors, the first termination resistors having a resistance higher than the characteristic impedence of the sense lines while the resistance of the second termination resistors is equal to or lower than the characteristic impedance of the sense lines.

Abstract translation: 一种用于核心存储器的感测电路，其中通过磁芯的感测线具有与放大器的近端连接，并且具有与第二终端电阻器连接的第一终端电阻器和远端，第一终端电阻器具有高于 而第二终端电阻的电阻等于或低于感测线的特征阻抗时感测线的特征阻抗。

公开(公告)号：US3774181A

公开(公告)日：1973-11-20

申请号：US3774181D

申请日：1972-07-13

Applicant: TECHNO MARKETING INC

Inventor： WELLS G ,  PERSONS P

IPC: G11C11/06 ,  H03K17/00 ,  H03K17/041 ,  H03K17/60 ,  G11C5/02 ,  G11C7/00

CPC classification number: G11C11/06007 ,  H03K17/04113 ,  H03K17/601 ,  H03K2217/0036

Abstract: A system for supplying a current to a core memory stack having substantial inductance including a transformer having a selectively variable primary/secondary turns ratio. The variable turns ratio permits the current buildup time interval in the core state to be minimized while reducing the power required to drive the stack.

Abstract translation: 一种用于向具有实质电感的核心存储器堆栈提供电流的系统，包括具有选择性可变的初级/次级匝数比的变压器。 可变匝数比允许在核心状态下的当前累积时间间隔最小化，同时减少驱动堆栈所需的功率。

公开(公告)号：US3740481A

公开(公告)日：1973-06-19

申请号：US3740481D

申请日：1971-09-29

Applicant: BOEING CO

Inventor： LEE S

IPC: G11C11/06 ,  G11C17/02 ,  H03K5/02 ,  H03K17/693 ,  H04J3/04

CPC classification number: H03K5/02 ,  G11C11/06007 ,  G11C17/02 ,  H03K17/693 ,  H04J3/047

Abstract: Sense line and sense amplifier configurations and circuits for coupling to magnetic memory elements. A sense line comprising a twisted pair of conductors provides coupling along its length to the memory elements. A pair of sense lines may be connected in series or parallel to provide sense signal output pulses of increased amplitude or provide redundancy in the sensing scheme. Further permutations and combinations of the twisted pair sense line provide sense signal output pulses of different amplitude to also provide, e.g., half select pulses. A sense amplifier system utilizes multiplexing techniques to simplify the sense scheme and reduce the amount of circuitry required between the sense lines and the buffer system.

Abstract translation: 感应线和读出放大器配置和电路，用于耦合到磁存储元件。 包括双绞导体线的传感线提供沿其长度的耦合到存储元件。 一对感测线可以串联或并联连接以提供增加振幅的感测信号输出脉冲或在感测方案中提供冗余。 双绞线检测线的进一步排列和组合提供不同幅度的感测信号输出脉冲，以提供例如半选择脉冲。 感测放大器系统利用复用技术来简化感测方案并减少感测线路和缓冲器系统之间所需的电路量。

公开(公告)号：US3737859A

公开(公告)日：1973-06-05

申请号：US3737859D

申请日：1972-03-21

Applicant: SIEMENS AG

Inventor： KADOW H

IPC: G11C11/06 ,  G01R15/12 ,  H04Q9/00

CPC classification number: G11C11/06007

Abstract: A selection matrix for a data memory having random access and which is dimensioned for a medium loading such as exists during normal operation and to which a control device is assigned which ensures that even in exceptional cases such as constant order the selection circuits are not overloaded the selection matrix employing a control system constructed as a selection matrix, two groups of control signal generators each corresponding to lines and columns of the selection matrix by which individual control signal generators may be selected.

Abstract translation: 一种用于具有随机存取的数据存储器的选择矩阵，其尺寸适用于在正常操作期间存在的介质负载，并且分配有控制装置的这种数据存储器的选择矩阵，其确保即使在诸如恒定顺序的特殊情况下，选择电路也不会过载 采用构成选择矩阵的控制系统的选择矩阵，两组控制信号发生器，每组控制信号发生器各自对应于可以选择各个控制信号发生器的选择矩阵的行和列。

公开(公告)号：US3707704A

公开(公告)日：1972-12-26

申请号：US3707704D

申请日：1970-09-09

Applicant: SIEMENS AG

Inventor： KADOW HERMANN

IPC: G06F11/00 ,  G11C11/06 ,  G11C11/24

CPC classification number: G06F11/0754 ,  G11C11/06007

Abstract: A selective circuit with optional access is provided with means for preventing overload of the circuit in case of repetitive or continuous call by the same address. The prevention of overload is effected by a technique which provides a simulation of the thermal state of the circuit. Also, a control unit is provided to limit the call succession of frequently used addresses.

Abstract translation: 具有可选访问的选择电路具有用于在由相同地址重复或连续呼叫的情况下防止电路过载的装置。 通过提供对电路的热状态的模拟的技术来实现防止过载。 此外，提供控制单元以限制频繁使用的地址的呼叫连续。

公开(公告)号：US3671949A

公开(公告)日：1972-06-20

申请号：US3671949D

申请日：1970-04-27

Applicant: GEN MOTORS CORP

Inventor： MCLEAN WILLIAM E ,  RUCH DAVID E

IPC: G11C7/02 ,  G11C11/06 ,  H03K17/0814 ,  G11C5/02

CPC classification number: G11C11/06007 ,  H03K17/08146

Abstract: Apparatus for supplying selection lines of a magnetic core memory with drive currents of uniform amplitude and configuration. The apparatus includes a pair of line selection switches at opposite ends of a selection line group for steering current from a source through a selected line and a current regulator that maintains the sum of the currents through the line at a constant level. The lines in the group are terminated by a set of alternately operable termination circuits, which set is common to all of the lines of a coordinate axis of the memory array. The termination circuit serve to damp voltage spikes, ringing oscillations and the inductive energy of the line upon energization and de-energization thereof and to maintain the lines of the memory stack at a fixed potential to prevent the lines from floating due to leakage currents and capacitive voltage build-ups that would establish the lines at different potentials during inactive or memory idle periods.

Abstract translation: 用于提供具有均匀幅度和配置的驱动电流的磁芯存储器选择线的装置。 该装置包括在选择线组的相对端处的一对线选择开关，用于从源极通过所选择的线转向电流;以及电流调节器，其将电流的总和保持在恒定电平。 组中的线由一组可交替操作的终端电路终止，该组被设置为存储器阵列的坐标轴的所有线是共同的。 终端电路用于在通电和断电时阻止电压尖峰，振荡振荡和线路的感应能量，并将存储器堆叠的线路保持在固定电位，以防止线路由于泄漏电流和电容 在不活动或内存空闲期间建立不同电位的电压积分。

公开(公告)号：US3660829A

公开(公告)日：1972-05-02

申请号：US3660829D

申请日：1970-07-15

Applicant: TECHNOLOGY MARKETING INC

Inventor： WELLS GEORGE H ,  PERSONS PERRY B

IPC: G11C11/06 ,  G11C5/02

CPC classification number: G11C11/06007

Abstract: A current steering system is described in the context of a multi-plane magnetic core memory stack. The system is designed to control a given end of a set of core drive lines and includes a pair of bipolar switches for each pair of lines. Each bipolar switch includes two diode pairs, each pair being connected in series through a common unipolar switch to form two switchable unidirectional current paths for each bipolar switch. One current path from each bipolar switch is connected between respective ones of their associated pair of drive lines and a switchable current source of a given polarity. The remaining two current paths of the pair of bipolar switches are connected between the same two lines and a switchable current source of the opposite polarity. In this way both bipolar switches participate in controlling the flow of current in each of a pair of drive lines.

Abstract translation: 在多平面磁芯存储器堆叠的上下文中描述了当前的转向系统。 该系统设计用于控制一组核心驱动线路的给定端，并且包括用于每对线路的一对双极开关。 每个双极开关包括两个二极管对，每对通过公共单极开关串联连接，以形成每个双极开关的两个可切换单向电流通路。 来自每个双极开关的一条电流路径连接在它们相关联的一对驱动线路中的相应的一个以及给定极性的可切换电流源。 一对双极开关的剩余两个电流路径连接在相同的两条线路和相反极性的可切换电流源之间。 以这种方式，双极开关参与控制一对驱动线路中的每一个中的电流流动。

公开(公告)号：US3651497A

公开(公告)日：1972-03-21

申请号：US3651497D

申请日：1970-06-29

Applicant: ELECTRONIC MEMORIES & MAGNETIC

Inventor： COOK WILLIAM M

IPC: G11C11/06 ,  G11C7/00

CPC classification number: G11C11/06007 ,  G11C11/06035

Abstract: A drive system for a magnetic core memory is disclosed using a pulsed current source to charge a selected group of lines common at one (sink) end and simultaneously raising the bias on the other open (drive) end. When the group has been charged sufficiently to forward bias a diode connected to a supply voltage VS, a termination resistor having a resistance approximately equal to the characteristic impedance of all lines common at the sink end, suppresses reflections and ringing. The output of the sink current source is connected to an isolating diode at the drive end of each line by a resistor, whereby the bias across the diode remains substantially constant as the lines are charged. A drive current source is selectively connected to one line of the selected (sink) group. A coupling diode in series with a resistor connected to a source of bias potential terminates the drive end of the selected line during the drive current rise time. When the sink current source is turned off after a memory cycle, a shunt switch is turned on to allow the selected group of lines to discharge to a level of approximately zero volts with respect to circuit ground. Two corresponding, but complementary sets of components are provided for read and write cycles with one shunt switch on during any given cycle to reduce voltage stresses on selection elements.

Abstract translation: 公开了一种用于磁芯存储器的驱动系统，其使用脉冲电流源来对在一个（接收）端部共同的所选择的一组线进行充电，同时提高另一个开路（驱动）端的偏置。 当组充分充电以将连接到电源电压VS的二极管正向偏置时，具有大致等于在接收端共同的所有线路的特性阻抗的电阻的终端电阻抑制反射和振铃。 灌电流源的输出通过电阻器连接到每行的驱动端处的隔离二极管，由此线路充电时，二极管的偏置保持基本恒定。 驱动电流源选择性地连接到所选择（接收）组的一行。 与连接到偏置电位源的电阻器串联的耦合二极管在驱动电流上升时间期间终止所选线路的驱动端。 当存储器周期之后，当电流源被关断时，分流开关导通，以允许所选择的线组相对于电路接地放电到大约零伏的水平。 在任何给定的周期内，为了读和写周期提供两个对应但互补的组件，其中一个并联开关导通，以减少选择元件上的电压。

公开(公告)号：US3651468A

公开(公告)日：1972-03-21

申请号：US3651468D

申请日：1970-12-09

Applicant: BELL TELEPHONE LABOR INC

Inventor： WAABEN SIGURD GUNTHER

IPC: G11C11/06 ,  G11C11/36 ,  H04Q3/00 ,  G11B5/00 ,  G11C7/00

CPC classification number: G11C11/06007 ,  G11C11/36

Abstract: An arrangement for decreasing the noise in tandem matrix access circuits which employ diodes to interconnect their primary and secondary sets of matrices. In particular, each rail circuit of the secondary matrix is coupled to its respective pair of rail circuits of the primary matrix by diodes which are oppositely poled with respect to one another. Connection of the rail circuits in this manner permits the nonselected rails of the secondary matrix to be coupled to ground through low impedances during selection of a particular rail of the matrix. As a result, leakage currents appearing in the nonselected rails are shunted to ground, thereby eliminating the noise effects of these currents in the matrix. In one embodiment of the invention, the two diodes coupled to each rail of the secondary matrix are charge-storage diodes. In another embodiment, one of the diodes is a charge-storage diode whereas the other is a Schottky diode.

Abstract translation: 用于降低串联矩阵存取电路中的噪声的装置，其使用二极管来互连其初级和次级矩阵。 特别地，次级矩阵的每个轨道电路通过相对于彼此相对极化的二极管耦合到其主要矩阵的相应的一对轨道电路。 以这种方式连接轨道电路允许在选择矩阵的特定轨道期间通过低阻抗将次级矩阵的非选择轨耦合到地。 结果，出现在非选择的轨道中的漏电流被分流到地，从而消除了这些电流在矩阵中的噪声影响。