公开(公告)号：US4223269A

公开(公告)日：1980-09-16

申请号：US829982

申请日：1977-09-01

申请人： Jean-Claude Barigot ,  Jean-Jacques Beau

发明人： Jean-Claude Barigot ,  Jean-Jacques Beau

IPC分类号： H04J3/12 ,  G06F7/00 ,  G11C19/00 ,  H03K5/18

CPC分类号： H04J3/12

摘要： Device for inserting several bits in a rhythmed digital train, comprising aosed looped shift register, the shift being controlled according to the rhythm of the train. The register receives, in parallel, the bits to be inserted, the write-in locations depending on the instant at which it is required to have these bits available in order to insert them in the train. Preferably, the train being subdivided into sub-groups (IT) of adjacent bits, the register comprises as many bistable elements as there are bits in a sub-group.

摘要翻译： 用于在节奏数字列车中插入几个比特的装置，包括计费的循环移位寄存器，所述班次根据列车的节奏被控制。 寄存器并行地接收要插入的位，写入位置取决于需要这些位可用的时刻，以便将它们插入到列车中。 优选地，列车被细分为相邻比特的子组（IT），该寄存器包括与子组中的比特一样多的双稳态元素。

公开(公告)号：US4214213A

公开(公告)日：1980-07-22

申请号：US845213

申请日：1977-10-25

申请人： Ronald G. Ferrie

发明人： Ronald G. Ferrie

IPC分类号： H04B7/08 ,  H03K5/18 ,  H03K5/20

CPC分类号： H04B7/082

摘要： A system which selects the highest quality signal from similar signals includes a signal quality detector for each of the signals and a comparator. Each detector provides an output level indicative of the quality of the signal and these signals indicative of the quality of the signal are sequentially provided to a first input of the comparator. The comparator is responsive to signal levels indicating a higher quality signal level than that of a reference level applied to a second input of the comparator for providing that signal out of the selecting system and providing a new reference signal level indicative of the higher quality signal to the second input of the comparator.

摘要翻译： 从类似信号中选择最高质量信号的系统包括用于每个信号的信号质量检测器和比较器。 每个检测器提供指示信号质量的输出电平，并且指示信号质量的这些信号被顺序地提供给比较器的第一输入端。 比较器响应于指示比施加到比较器的第二输入的参考电平更高的质量信号电平的信号电平，以将该信号提供出选择系统，并将指示较高质量信号的新参考信号电平提供给 比较器的第二个输入。

公开(公告)号：US4198608A

公开(公告)日：1980-04-15

申请号：US921961

申请日：1978-07-05

申请人： William Comley

发明人： William Comley

IPC分类号： H03M1/00 ,  H03K13/32 ,  H03K5/18 ,  H03K13/02

CPC分类号： H03M1/0872

摘要： A glitch detector and trap circuit is disclosed for removing a glitch generated by a digital-to-analog (D/A) converter due to an error in one or more bits of the input digital signal. The analog output signal is delayed by one sample period. The converter output signal is then subtracted from the delayed converter output signal. This difference signal is passed through a full-wave precision rectifier. Thereafter, the notified signal is clipped at a predetermined trigger level so that a glitch will cause an output pulse. The output pulse caused by a glitch is used to operate a monostable circuit. The monostable circuit in turn, is utilized to change a track and store amplifier from its track mode to the store mode. In this manner, the track and store amplifier will not pass the glitch, but will remain at its previous setting. A rise-time delay circuit is interposed ahead of the track and store amplifier so that it will not respond instantaneously to the next sample pulse before its store mode is initiated.

摘要翻译： 公开了一种毛刺检测器和陷波电路，用于消除由于输入数字信号的一个或多个位中的错误而由数模（D / A）转换器产生的毛刺。 模拟输出信号延迟一个采样周期。 然后从延迟转换器输出信号中减去转换器输出信号。 该差分信号通过全波精密整流器。 此后，通知的信号以预定的触发电平被削波，使得毛刺产生输出脉冲。 由毛刺引起的输出脉冲用于操作单稳态电路。 单稳态电路又用来改变轨道并将放大器从其轨道模式存储到存储模式。 以这种方式，轨道和商店放大器不会通过毛刺，但将保持在其先前的设置。 上升时间延迟电路插在轨道和存储放大器之前，使得它在其存储模式被启动之前不会立即响应于下一个采样脉冲。

公开(公告)号：US4197507A

公开(公告)日：1980-04-08

申请号：US894462

申请日：1978-04-07

申请人： Robert E. Cunningham ,  Philip H. Bush

发明人： Robert E. Cunningham ,  Philip H. Bush

IPC分类号： G11B5/027 ,  H03K5/13 ,  H03K5/153 ,  H03K5/18 ,  H03K13/32

CPC分类号： G11B5/027

摘要： A supressing pulse synthesizer for supplying the proper average number of nchronization pulses from a reproduced reference signal to an analog to digital converter utilized to convert analog data present on a magnetic tape to digital data.

摘要翻译： 一种抑制脉冲合成器，用于从再现的参考信号向用于将存在于磁带上的模拟数据转换为数字数据的模数转换器提供适当的平均数量的同步脉冲。

公开(公告)号：US4152655A

公开(公告)日：1979-05-01

申请号：US837724

申请日：1977-09-29

申请人： Bernd Przybyla ,  Peter J. Schmidt

发明人： Bernd Przybyla ,  Peter J. Schmidt

IPC分类号： H03K5/19 ,  H03K5/18

CPC分类号： H03K5/19

摘要： Omission of a pulse in an otherwise regular pulse sequence, such as may be produced by omission of a tooth of a rotating gear that is used to generate a pulse sequence through a pick-up, is utilized after the manner of a special framing pulse, saving the complications of providing a framing pulse, especially in gasoline engine ignition timing. A counter is started with the beginning of every pulse of the sequence and is operated at a multiple of the sequence frequency. If the frequency varies, the count status when the next pulse arrives will vary slightly and this variation may be caused to change the initial condition for the beginning of each count cycle to keep the repetitive counting generally in step with the varying frequency. When a pulse of the sequence is skipped, however, the repetitive counter goes into a range of content states well beyond those produced by frequency variation and a decoding stage with an appropriate threshold value stored therein gives an indication that a pulse has been missed, which prepares a response to the next pulse which will produce a timing reference signal instead of a correction to the circuits following the frequency of the observed pulse sequence. The latter and also an engine load sensor address an ROM to provide the timing angle signal.

摘要翻译： 在特殊成帧脉冲的方式之后，利用例如可以通过省略用于通过拾波器产生脉冲序列的旋转齿轮的齿来产生否则规则脉冲序列中的脉冲， 节省提供框架脉冲的并发症，特别是在汽油发动机点火正时。 计数器以序列的每个脉冲的开始开始，并以序列频率的倍数运行。 如果频率变化，则当下一个脉冲到达时的计数状态会略有变化，这种变化可能导致改变每个计数周期开始的初始条件，以保持重复计数一般与变化的频率一致。 然而，当跳过序列的脉冲时，重复计数器进入远远超过由频率变化产生的内容状态的范围，并且具有存储在其中的适当阈值的解码级给出脉冲已被错过的指示，哪个 准备对下一个脉冲的响应，该脉冲将产生定时参考信号，而不是根据观察到的脉冲序列的频率对电路进行校正。 后者以及发动机负载传感器地址ROM以提供定时角度信号。

公开(公告)号：US4151472A

公开(公告)日：1979-04-24

申请号：US851374

申请日：1977-11-14

申请人： Eiji Watanabe ,  Junichi Onozawa ,  Jouji Tanaka ,  Takazo Takahashi ,  Tsuneo Kitamura ,  Hiroshi Yamada ,  Hiroshi Noguchi ,  Yukio Ueno

发明人： Eiji Watanabe ,  Junichi Onozawa ,  Jouji Tanaka ,  Takazo Takahashi ,  Tsuneo Kitamura ,  Hiroshi Yamada ,  Hiroshi Noguchi ,  Yukio Ueno

IPC分类号： H04Q1/30 ,  G01R15/09 ,  G01R23/00 ,  G08B3/10 ,  H04Q7/16 ,  H03K17/26 ,  H03K5/18

CPC分类号： G01R15/09 ,  G01R23/005 ,  G08B3/1008

摘要： In a selective calling circuit including a band-pass filter which may be constituted by an active filter, and a power source for energizing the filter, a control signal is generated which has a predetermined duration in accordance with the output of the band-pass filter at a point of time whereat the output of the band-pass filter reaches a predetermined level. In response to the control signal, there is established a state in which the center frequency of the band-pass filter can be changed, and the output of the power source is changed from a first level to a second level for a period of time substantially corresponding to the predetermined duration of the control signal. At the aforementioned first level, the band-pass filter may be energized, while at the second level, it may be deenergized.

摘要翻译： 在包括可由有源滤波器构成的带通滤波器和用于激励滤波器的电源的选呼电路中，产生根据带通滤波器的输出具有预定持续时间的控制信号 在带通滤波器的输出达到预定电平的时间点。 响应于控制信号，建立了可以改变带通滤波器的中心频率并且将电源的输出从第一电平改变到第二电平一段时间的状态 对应于控制信号的预定持续时间。 在上述第一级，带通滤波器可以被激励，而在第二级，它可以被断电。

公开(公告)号：US4107556A

公开(公告)日：1978-08-15

申请号：US796334

申请日：1977-05-12

申请人： Roger Green Stewart ,  Sargent Sheffield Eaton, Jr.

发明人： Roger Green Stewart ,  Sargent Sheffield Eaton, Jr.

IPC分类号： G11C11/404 ,  G11C11/4091 ,  H03K3/356 ,  H03K5/02 ,  H03K5/18 ,  G11C7/06 ,  H03K3/286 ,  H03K3/353

CPC分类号： H03K5/023 ,  G11C11/404 ,  G11C11/4091 ,  H03K3/356147

摘要： A sense circuit suitable for use with semiconductor memory arrays which, in contrast to sense circuits of similar type, exhibits no voltage offset in the latched condition between the input-output (I/O) nodes and the supply lines. The sense circuit includes first and second complementary inverters with inputs connected to first and second I/O nodes, respectively, and with outputs capable of being clamped to one or the other of the two supply lines powering the inverters. Selectively and sequentially enabled cross-coupling transmission gates are connected between the output of each inverter and the input to the other inverter, and selectively enabled biasing transmission gates are connected between the input and output of each inverter. In the operation of the circuit, the two input nodes are first precharged to a predetermined value by enabling the biasing gates. A signal is then applied to one I/O node causing its potential to vary from its quiescent value. Then, the cross-coupling gate connected to the output of the inverter whose input is connected to the one I/O node is first enabled and, subsequently, the other cross-coupling gate is enabled. When the two cross-coupling gates are enabled, the inverters are latched and form a flip flop with the first I/O node clamped to the supply line having the same binary signal and the second I/O node clamped to the other power supply line.

摘要翻译： 适用于半导体存储器阵列的感测电路，其与相似类型的感测电路相反，在输入 - 输出（I / O）节点和电源线之间的锁存状态下不显示电压偏移。 感测电路包括第一和第二互补逆变器，其输入分别连接到第一和第二I / O节点，并且具有能够被钳位到为逆变器供电的两个电源线中的一个或另一个的输出。 在每个逆变器的输出端与另一个反相器的输入端之间连接有选择性顺序使能的交叉耦合传输门，并且有选择地使能的偏置传输门连接在每个逆变器的输入和输出之间。 在电路的操作中，通过使偏置栅极能够使两个输入节点首先被预充电到预定值。 然后将信号施加到一个I / O节点，导致其电位从静态值变化。 然后，连接到其输入连接到一个I / O节点的逆变器的输出的交叉耦合栅极首先被使能，并且随后使能另一个交叉耦合门。 当两个交叉耦合门被使能时，反相器被锁存并形成触发器，其中第一I / O节点钳位到具有相同二进制信号的电源线，并且第二I / O节点钳位到另一个电源线 。

公开(公告)号：US4104545A

公开(公告)日：1978-08-01

申请号：US821821

申请日：1977-08-04

申请人： Gary S. Dallas ,  Richard J. Pittaro

发明人： Gary S. Dallas ,  Richard J. Pittaro

IPC分类号： G01R29/02 ,  H03K5/1532 ,  H03K5/18 ,  H03K5/20

CPC分类号： G01R29/02 ,  H03K5/1532

摘要： A pulse peak detector circuit for use in measuring the peak amplitude of a fast rise time, narrow pulse width pulse as in commonly encountered in an ultrasonic non-destructive testing instrument includes two amplifying means. A first amplifying means compensates small amplitude signals for the characteristics of a unidirectional current conducting means forming a part of the detector circuit while the second amplifying means provides conventional amplification of the applied signal.

摘要翻译： 用于测量超声无损检测仪器中通常遇到的快速上升时间，窄脉冲宽度脉冲的峰值振幅的脉冲峰值检测器电路包括两个放大装置。 第一放大装置补偿小幅度信号用于形成检测器电路的一部分的单向电流传导装置的特性，而第二放大装置提供所施加的信号的常规放大。

公开(公告)号：US4081701A

公开(公告)日：1978-03-28

申请号：US691735

申请日：1976-06-01

申请人： Lionel S. White, Jr. ,  Hugh P. McAdams ,  Donald J. Redwine

发明人： Lionel S. White, Jr. ,  Hugh P. McAdams ,  Donald J. Redwine

IPC分类号： G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  H03K5/20 ,  G11C11/40 ,  H03K3/286 ,  H03K5/18

CPC分类号： G11C11/408 ,  G11C11/4091 ,  G11C11/4093

摘要： A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. The load transistors in each bistable circuit have clock voltages applied to their gates after an initial sensing period, so the initial sensing is done without loads for the bistable circuit. After this initial period, the load transistors are turned on by boosting capacitors. Then, fixed biased transistors shunting the gates of the load device to the digit lines function to turn off the load device on the zero logic level side.

摘要翻译： MOS集成电路类型的随机存取存储器件采用在每列的中心具有双稳态读出放大器电路的单晶体管存储单元的行和列阵列。 每个双稳态电路中的负载晶体管在初始感测周期之后具有施加到其栅极的时钟电压，因此初始感测在双稳态电路的负载下完成。 在该初始时段之后，负载晶体管通过升压电容器导通。 然后，将负载装置的栅极分流到数字线的固定偏压晶体管起到关闭零逻辑电平侧的负载装置的作用。

公开(公告)号：US4080589A

公开(公告)日：1978-03-21

申请号：US583147

申请日：1975-06-02

申请人： Ralph LeRoy Kline

发明人： Ralph LeRoy Kline

IPC分类号： G01R23/15 ,  H03K5/19 ,  H03K5/18

CPC分类号： G01R23/15 ,  H03K5/19

摘要： An initial error indicated by a pulse at the binary input is applied through a gating circuit to trigger a monostable multivibrator (one-shot) to start a timing interval. The output of the one-shot is applied to a second gating circuit which inhibits the first gating circuit to prevent retriggering of the one-shot. Subsequent error pulses are then applied directly to a counting mechanism which counts the errors which occur during the predetermined time interval established by the one-shot. An acceptable error density is established by the predetermined time interval for the one-shot in relation to the number of errors that would occur during this predetermined time interval. If the number of errors which occur exceeds the acceptable error density, the counting circuit puts out a signal which may be applied to an alarm (or framing) circuit. Once the error counter produces an output, i.e., exceeds the acceptable error density, the counter applies a binary indication to the second gating circuit which causes the first gating circuit to retrigger the one-shot. Further, each error pulse which occurs before the one-shot times out will now trigger the one-shot. In order for the circuit to reset, an error-free period, equal to the period of the one-shot, must occur.

摘要翻译： 由二进制输入端的脉冲指示的初始误差通过门控电路施加，以触发单稳态多谐振荡器（单稳态）以开始定时间隔。 一次性的输出被施加到第二门控电路，其阻止第一门控电路防止单触发的重新触发。 然后将随后的误差脉冲直接施加到计数机构，该计数机构对由单次拍摄建立的预定时间间隔期间发生的误差进行计数。 相对于在该预定时间间隔内将发生的错误数量，针对单触发的预定时间间隔建立可接受的误差密度。 如果出现的错误数超过可接受的误差密度，则计数电路会输出可能应用于报警（或成帧）电路的信号。 一旦错误计数器产生输出，即超过可接受的误差密度，则计数器向第二选通电路施加二进制指示，使得第一门控电路重新触发单触发。 此外，在单次超时之前发生的每个错误脉冲现在将触发一次。 为了使电路复位，必须发生等于单次触发周期的无错误周期。