公开(公告)号：US08633558B2

公开(公告)日：2014-01-21

申请号：US12981640

申请日：2010-12-30

Applicant: Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

Inventor： Ta-Hsuan Lin ,  Chuan-Jin Shiu ,  Chia-Ming Cheng ,  Tsang-Yu Liu

IPC: H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.

Abstract translation: 该实施例提供了用于芯片的封装结构及其制造方法。 用于芯片的封装结构包括具有衬底和焊盘结构的芯片。 该芯片具有上表面和下表面。 上包装层覆盖芯片的上表面。 间隔层位于上包装层和芯片之间。 导电路径电连接到接合焊盘结构。 防反射层设置在间隔层和上包装层之间。 重叠区域在抗反射层和间隔层之间。

公开(公告)号：US20110156191A1

公开(公告)日：2011-06-30

申请号：US12981640

申请日：2010-12-30

Applicant: Ta-Hsuan LIN ,  Chuan-Jin SHIU ,  Chia-Ming CHENG ,  Tsang-Yu LIU

Inventor： Ta-Hsuan LIN ,  Chuan-Jin SHIU ,  Chia-Ming CHENG ,  Tsang-Yu LIU

IPC: H01L31/0216 ,  H01L31/18

CPC classification number: H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiment provides a package structure for a chip and a method for fabricating the same. The package structure for the chip includes a chip having a substrate and a bonding pad structure. The chip has an upper surface and a lower surface. An upper packaging layer covers the upper surface of the chip. A spacer layer is between the upper packaging layer and the chip. A conductive path is electrically connected to the bonding pad structure. An anti-reflective layer is disposed between the spacer layer and the upper packaging layer. An overlapping region is between the anti-reflective layer and the spacer layer.

Abstract translation: 该实施例提供了用于芯片的封装结构及其制造方法。 用于芯片的封装结构包括具有衬底和焊盘结构的芯片。 该芯片具有上表面和下表面。 上包装层覆盖芯片的上表面。 间隔层位于上包装层和芯片之间。 导电路径电连接到接合焊盘结构。 防反射层设置在间隔层和上包装层之间。 重叠区域在抗反射层和间隔层之间。