公开(公告)号：US06486651B1

公开(公告)日：2002-11-26

申请号：US09721135

申请日：2000-11-22

申请人： Jong-soo Lee ,  Kye-hyun Kyung ,  Dae-sun Kim ,  Hyo-jin Oh ,  Sang-chul Kim ,  Tae-seek Son

发明人： Jong-soo Lee ,  Kye-hyun Kyung ,  Dae-sun Kim ,  Hyo-jin Oh ,  Sang-chul Kim ,  Tae-seek Son

IPC分类号： G01R2312

CPC分类号： G11C29/12015 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/14

摘要： Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.

摘要翻译： 集成电路装置及其操作方法包括可以在正常操作模式期间和在测试模式期间以高频率操作的延迟锁定环（DLL）电路。 测试模式可以是例如用于进行老化测试。 例如，集成电路装置可以包括产生响应于测试模式信号的控制信号的DLL控制电路。 振荡器电路可以产生响应于测试模式信号的时钟信号。 该时钟信号可以是高频时钟信号，例如用于在正常操作模式期间驱动DLL电路的时钟信号。 响应于时钟信号的DLL电路可以被配置为基于控制信号在测试模式或正常操作模式中操作。 通过以高频产生时钟信号，可以在老化测试期间评估DLL电路，例如在与正常操作期间的条件相当的条件下。