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1.发明授权Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same 失效制造半导体集成电路的方法，图案检测方法和用于半导体对准的系统和减少的步进曝光在其中使用
公开(公告)号：US5094539A
公开(公告)日：1992-03-10
申请号：US313180
申请日：1989-02-21
IPC分类号： G03F9/00
CPC分类号： G03F9/70
摘要： According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h- line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
摘要翻译： 根据本发明，在使用诸如水银灯的g-，i-或h-线的单色光在晶片的曝光中在半导体集成电路晶片和掩模或掩模版之间进行对准时，使用还原 步进曝光系统，从晶片上的预定图案的光被取出到离轴位置，并根据透镜方法观察; 在这种情况下，作为本发明的特征，观察光从掩模版的下方取出并通过色像差校正透镜，从而允许使用多色或连续的光谱光。
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2.发明授权Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same 失效制造半导体集成电路的方法，图案检测方法以及用于半导体对准的系统和减少的步进曝光用于其中
公开(公告)号：US5432608A
公开(公告)日：1995-07-11
申请号：US111310
申请日：1993-08-24
CPC分类号： G03F9/70
摘要： According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to Through-the-Lens method; in this case as a characteristic feature of the invention, the observation light taken out from below the reticle is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
摘要翻译： 根据本发明，在采用诸如水银灯的g-，i-或h-线的单色光的晶片的曝光中，在半导体集成电路晶片和掩模或掩模版之间进行对准时，使用还原 步进曝光系统，从晶片上的预定图案的光线取出到离轴位置，并根据透镜法进行观察; 在这种情况下，作为本发明的特征，从掩模版下方取出的观察光通过色像差校正透镜，从而允许使用多色或连续光谱光。
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3.发明授权Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same 失效制造半导体集成电路的方法，图案检测方法以及用于半导体对准的系统和减少的步进曝光用于其中
公开(公告)号：US5260771A
公开(公告)日：1993-11-09
申请号：US811059
申请日：1991-12-20
CPC分类号： G03F9/70
摘要： According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the, observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
摘要翻译： 根据本发明，在采用诸如水银灯的g-，i-或h-线的单色光的晶片的曝光中，在半导体集成电路晶片和掩模或掩模版之间进行对准时，使用还原 步进曝光系统，从晶片上的预定图案的光被取出到离轴位置，并根据透镜方法观察; 在这种情况下，作为本发明的特征，观察光从掩模版的下方取出并通过色像差校正透镜，从而允许使用多色或连续光谱光。
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