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公开(公告)号：US06894790B2
公开(公告)日：2005-05-17
申请号：US10291675
申请日：2002-11-12
申请人： Yasuhiro Mitsui , Yasutsugu Usami , Isao Kawata , Yuya Toyoshima , Tadashi Otaka , Nobuyuki Iriki
发明人： Yasuhiro Mitsui , Yasutsugu Usami , Isao Kawata , Yuya Toyoshima , Tadashi Otaka , Nobuyuki Iriki
IPC分类号： G01Q30/04 , H01L23/544 , G01B11/02
CPC分类号： H01L22/34
摘要： A test pattern formed in a scribe line area of a wafer is irradiated with a light beam to measure the width thereof; the test pattern is irradiated with an electron beam so as to measure the width thereof; an amount of change in the width of the test pattern is calculated; a dummy pattern having the same width as that of a semiconductor device of the wafer is irradiated with an electron beam to measure the width thereof; and the width of a pattern is estimated by the use of the calculated amount of width change so as to determine the shape of the pattern. Thus, a shape measuring system and method capable of determining the shape of a micropattern in a semiconductor device without changing the dimensions of the micropattern can be provided.
摘要翻译： 用光束照射在晶片的划线区域中形成的测试图案，以测量其宽度; 用电子束照射测试图案以测量其宽度; 计算测试图案的宽度的变化量; 用电子束照射具有与晶片的半导体器件相同的宽度的虚拟图案，以测量其宽度; 并且通过使用计算出的宽度变化量来估计图案的宽度，以便确定图案的形状。 因此，可以提供能够在不改变微图案的尺寸的情况下确定半导体器件中的微图案的形状的形状测量系统和方法。
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公开(公告)号：US20050182595A1
公开(公告)日：2005-08-18
申请号：US11102703
申请日：2005-04-11
申请人： Yasuhiro Mitsui , Yasutsugu Usami , Isao Kawata , Yuya Toyoshima , Tadashi Otaka , Nobuyuki Iriki
发明人： Yasuhiro Mitsui , Yasutsugu Usami , Isao Kawata , Yuya Toyoshima , Tadashi Otaka , Nobuyuki Iriki
IPC分类号： G01Q30/04 , H01L23/544 , G06F15/00
CPC分类号： H01L22/34
摘要： A test pattern formed in a scribe line area of a wafer is irradiated with a light beam to measure the width thereof; the test pattern is irradiated with an electron beam so as to measure the width thereof; an amount of change in the width of the test pattern is calculated; a dummy pattern having the same width as that of a semiconductor device of the wafer is irradiated with an electron beam to measure the width thereof; and the width of a pattern is estimated by the use of the calculated amount of width change so as to determine the shape of the pattern. Thus, a shape measuring system and method capable of determining the shape of a micropattern in a semiconductor device without changing the dimensions of the micropattern can be provided.
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3.发明授权公开(公告)号：US06716648B2
公开(公告)日：2004-04-06
申请号：US10025458
申请日：2001-12-26
申请人： Nobuyuki Iriki
发明人： Nobuyuki Iriki
IPC分类号： H01L2166
CPC分类号： G03F7/70533 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： The efficiency is improved for a lithography step in a process of manufacturing semiconductor integrated circuits. For each semiconductor wafer, the method has a step of depositing a photosensitive organic film, a step of performing exposure processing, a step of performing development processing, a step of conducting a test, and a consistent processing step for removing the photosensitive organic film of a semiconductor wafer determined as nonstandard in the test in the processing unit for depositing the photosensitive organic film, and returning again to the step of depositing the photosensitive organic film to regenerate the semiconductor wafer. During the regeneration processing for the semiconductor wafer, other processing is automatically performed in parallel for other semiconductor wafers of the plurality of semiconductor wafers in a system for performing the consistent processing.
摘要翻译： 在制造半导体集成电路的过程中的光刻步骤的效率得到改善。 对于每个半导体晶片，该方法具有沉积光敏有机膜的步骤，进行曝光处理的步骤，进行显影处理的步骤，进行测试的步骤以及用于去除感光性有机膜的一致的处理步骤 在用于沉积光敏有机膜的处理单元中的测试中被确定为非标准的半导体晶片，并且再次返回到沉积感光有机膜以再生半导体晶片的步骤。 在用于半导体晶片的再生处理中，在用于执行一致处理的系统中，对多个半导体晶片的其它半导体晶片的并行自动执行其它处理。
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4.发明授权Semiconductor integrated circuit device fabrication method and its fabrication apparatus 失效半导体集成电路器件制造方法及其制造装置
公开(公告)号：US5497331A
公开(公告)日：1996-03-05
申请号：US257262
申请日：1994-06-08
IPC分类号： H01L21/677 , G05B13/02 , H01L21/02 , H01L21/027 , H01L21/30 , H01L21/66 , G06F19/00 , G06F17/60
CPC分类号： H01L22/20 , Y10S706/90 , Y10S706/904
摘要： A semiconductor integrated circuit device fabrication technique improves the accuracy of element qualities by considering the influence of interaction of element quality parameters in the quality control of semiconductor fabrication processes and also by improving the product yield estimation accuracy so that the production efficiency can be improved. An initial value of a membership function is first set and then a plurality of element quality parameters and a combined quality parameter are expressed by membership functions in fuzzy control in a semiconductor fabrication apparatus for automating a fabrication method by connecting a computer with various measuring instruments and various processors by communication devices. Moreover, the combined quality parameters are fuzzy-inferred from the element quality parameters using these membership functions, inference rules are adjusted by data of the actual processes, the membership functions of the obtained element quality parameters are converted into an element quality control standard, and the semiconductor integrated circuit device fabrication processes are controlled in accordance with the standard.
摘要翻译： 半导体集成电路器件制造技术通过考虑元件质量参数在半导体制造工艺的质量控制中的相互作用的影响以及通过提高产品产量估算精度来提高元件质量的精度，从而可以提高生产效率。 首先设置隶属度函数的初始值，然后在半导体制造装置中通过模糊控制中的隶属函数表示多个元素质量参数和组合质量参数，用于通过将计算机与各种测量仪器连接来自动化制造方法，以及 各种处理器由通信设备。 此外，使用这些隶属函数从元素质量参数中模糊组合的质量参数，推理规则由实际过程的数据进行调整，所获得的元素质量参数的隶属函数被转换为元素质量控制标准， 根据标准控制半导体集成电路器件制造工艺。
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5.发明授权Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same 失效制造半导体集成电路的方法，图案检测方法和用于半导体对准的系统和减少的步进曝光在其中使用
公开(公告)号：US5094539A
公开(公告)日：1992-03-10
申请号：US313180
申请日：1989-02-21
IPC分类号： G03F9/00
CPC分类号： G03F9/70
摘要： According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h- line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
摘要翻译： 根据本发明，在使用诸如水银灯的g-，i-或h-线的单色光在晶片的曝光中在半导体集成电路晶片和掩模或掩模版之间进行对准时，使用还原 步进曝光系统，从晶片上的预定图案的光被取出到离轴位置，并根据透镜方法观察; 在这种情况下，作为本发明的特征，观察光从掩模版的下方取出并通过色像差校正透镜，从而允许使用多色或连续的光谱光。
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公开(公告)号：US07130063B2
公开(公告)日：2006-10-31
申请号：US11102703
申请日：2005-04-11
申请人： Yasuhiro Mitsui , Yasutsugu Usami , Isao Kawata , Yuya Toyoshima , Tadashi Otaka , Nobuyuki Iriki
发明人： Yasuhiro Mitsui , Yasutsugu Usami , Isao Kawata , Yuya Toyoshima , Tadashi Otaka , Nobuyuki Iriki
IPC分类号： G01B11/04
CPC分类号： H01L22/34
摘要： A test pattern formed in a scribe line area of a wafer is irradiated with a light beam to measure the width thereof; the test pattern is irradiated with an electron beam so as to measure the width thereof; an amount of change in the width of the test pattern is calculated; a dummy pattern having the same width as that of a semiconductor device of the wafer is irradiated with an electron beam to measure the width thereof; and the width of a pattern is estimated by the use of the calculated amount of width change so as to determine the shape of the pattern. Thus, a shape measuring system and method capable of determining the shape of a micropattern in a semiconductor device without changing the dimensions of the micropattern can be provided.
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7.发明授权Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same 失效制造半导体集成电路的方法，图案检测方法以及用于半导体对准的系统和减少的步进曝光用于其中
公开(公告)号：US5432608A
公开(公告)日：1995-07-11
申请号：US111310
申请日：1993-08-24
CPC分类号： G03F9/70
摘要： According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to Through-the-Lens method; in this case as a characteristic feature of the invention, the observation light taken out from below the reticle is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
摘要翻译： 根据本发明，在采用诸如水银灯的g-，i-或h-线的单色光的晶片的曝光中，在半导体集成电路晶片和掩模或掩模版之间进行对准时，使用还原 步进曝光系统，从晶片上的预定图案的光线取出到离轴位置，并根据透镜法进行观察; 在这种情况下，作为本发明的特征，从掩模版下方取出的观察光通过色像差校正透镜，从而允许使用多色或连续光谱光。
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8.发明授权Method of making semiconductor integrated circuit, pattern detecting method, and system for semiconductor alignment and reduced stepping exposure for use in same 失效制造半导体集成电路的方法，图案检测方法以及用于半导体对准的系统和减少的步进曝光用于其中
公开(公告)号：US5260771A
公开(公告)日：1993-11-09
申请号：US811059
申请日：1991-12-20
CPC分类号： G03F9/70
摘要： According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h-line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the, observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
摘要翻译： 根据本发明，在采用诸如水银灯的g-，i-或h-线的单色光的晶片的曝光中，在半导体集成电路晶片和掩模或掩模版之间进行对准时，使用还原 步进曝光系统，从晶片上的预定图案的光被取出到离轴位置，并根据透镜方法观察; 在这种情况下，作为本发明的特征，观察光从掩模版的下方取出并通过色像差校正透镜，从而允许使用多色或连续光谱光。
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