公开(公告)号：US08223265B2

公开(公告)日：2012-07-17

申请号：US11698754

申请日：2007-01-26

申请人： Takemi Beppu ,  Naoyuki Konno

发明人： Takemi Beppu ,  Naoyuki Konno

IPC分类号： H04N5/06 ,  H04N5/04 ,  H03L7/00

CPC分类号： H04N5/10

摘要： Timing of internally generated horizontal synchronization signal and vertical synchronization signal is shifted. An internal clock is synchronized with a horizontal synchronization signal separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon. A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, a vertical synchronization signal is obtained in a VS output circuit 18. Here, the VS output circuit 18 internally has a delay circuit, and the timing of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS.

摘要翻译： 内部产生的水平同步信号和垂直同步信号的定时被移位。 内部时钟与在同步分离电路10中分离的水平同步信号同步，基于H计数电路14生成H复位信号，并且基于此产生水平同步信号。 在同步分离电路10中分离的垂直同步信号由在H倒数计时电路14中获得的2×FH信号归一化，并且基于获得的V复位信号，在VS输出电路18中获得垂直同步信号。这里 VS输出电路18内部具有延迟电路，并且要输出的垂直同步信号VS的定时与水平同步信号HS的定时相位移。

公开(公告)号：US20070177057A1

公开(公告)日：2007-08-02

申请号：US11698754

申请日：2007-01-26

申请人： Takemi Beppu ,  Naoyuki Konno

发明人： Takemi Beppu ,  Naoyuki Konno

IPC分类号： H04N5/06

CPC分类号： H04N5/10

摘要： Timing of internally generated horizontal synchronization signal and vertical synchronization signal is shifted. An internal clock is synchronized with a horizontal synchronization signal separated in a synchronization separation circuit 10, an H reset signal is generated based thereon in an H countdown circuit 14, and a horizontal synchronization signal is generated based thereon. A vertical synchronization signal separated in the synchronization separation circuit 10 is normalized by a 2×FH signal obtained in the H countdown circuit 14, and based on an obtained V reset signal, a vertical synchronization signal is obtained in a VS output circuit 18. Here, the VS output circuit 18 internally has a delay circuit, and the timing of a vertical synchronization signal VS to be output is shifted from that of a horizontal synchronization signal HS.

摘要翻译： 内部产生的水平同步信号和垂直同步信号的定时被移位。 内部时钟与在同步分离电路10中分离的水平同步信号同步，基于H计数电路14生成H复位信号，并且基于此产生水平同步信号。 在同步分离电路10中分离的垂直同步信号由在H倒数计时电路14中获得的2xFH信号归一化，并且基于获得的V复位信号，在VS输出电路18中获得垂直同步信号。 这里，VS输出电路18内部具有延迟电路，并且要输出的垂直同步信号VS的定时从水平同步信号HS的定时偏移。

公开(公告)号：US06812728B2

公开(公告)日：2004-11-02

申请号：US10650387

申请日：2003-08-28

申请人： Takemi Beppu

发明人： Takemi Beppu

IPC分类号： G01R3126

CPC分类号： G01R31/2853

摘要： There has been no appropriate means to test connections between two integrated circuits packaged in a single semiconductor package. This invention offers a test method on internal connections in a semiconductor package housing a first integrated circuit and a second integrated circuit connected with each other, including applying a test signal to a first pin of the semiconductor package, applying the test signal from the first pin to the first integrated circuit, applying a first signal generated in the first integrated circuit from the test signal to the second integrated circuit, applying a second signal generated in the second integrated circuit from the first signal back to the first integrated circuit, leading a third signal generated in the first integrated circuit from the second signal out of the semiconductor package through a second pin of the semiconductor package and confirming connections between the first integrated circuit and the second integrated circuit by verifying the third signal led out of the semiconductor package.

公开(公告)号：US06710821B1

公开(公告)日：2004-03-23

申请号：US09344751

申请日：1999-06-25

申请人： Ikuo Osawa ,  Takemi Beppu ,  Kenichi Nakajima

发明人： Ikuo Osawa ,  Takemi Beppu ,  Kenichi Nakajima

IPC分类号： H04N973

CPC分类号： H04N9/73

摘要： A white balance adjusting apparatus includes a test signal source 13 for generating a black signal for testing and a white signal for testing, a first impedance means 1 for converting currents flowing through three drive transistors for amplifying primary color R, G, B signals into voltages, a second impedance means 5 connected in parallel with the first impedance means, a switch 6 which is selectively closed to flow a current through the second impedance means, a reference voltage source 7 for generating a first reference voltage at the time of performing the cut-off adjustment and a second reference voltage at the time of performing the drive adjustment, a comparator 8 for comparing the levels between the reference voltages of the reference voltage sources and the output voltage converted by the first or second impedance means, and a microcomputer 75 which generates a control signal for adjusting the white balance on the basis of the output signal of the comparator and adjusts the DC level and the AC level of each of the primary colors of R, G, B.

摘要翻译： 白平衡调整装置包括用于产生用于测试的黑色信号的测试信号源13和用于测试的白色信号;第一阻抗装置1，用于转换流过三个驱动晶体管的电流，用于将原色R，G，B信号放大为电压 ，与第一阻抗装置并联连接的第二阻抗装置5，选择性地闭合以使流过第二阻抗装置的电流的开关6，用于在执行切割时产生第一参考电压的参考电压源7 用于比较参考电压源的参考电压与由第一或第二阻抗装置转换的输出电压之间的电平的比较器8和微机75 其基于比较器的输出信号产生用于调整白平衡的控制信号，并调整DC 水平和R，G，B各原色的交流电平。

公开(公告)号：US5757632A

公开(公告)日：1998-05-26

申请号：US799868

申请日：1997-02-14

申请人： Takemi Beppu ,  Hiroshi Matsui

发明人： Takemi Beppu ,  Hiroshi Matsui

IPC分类号： H02M3/07

CPC分类号： H02M3/07

摘要： A saw-wave generator (51) creates a saw-wave. Two comparators (COMP1, C0MP2) obtain two control signals having different duty ratios. Using these two control signals, two transistors (54, 56) are switched ON and OFF in complement and at voltage boost output when transistor (54) is OFF and transistor (56) is ON, transistor (57) is switched from ON to OFF and transistor (59) is switched from ON to OFF. A quadrupled voltage is thereby obtained.

摘要翻译： 锯波发生器（51）产生锯波。 两个比较器（COMP1，C0MP2）获得具有不同占空比的两个控制信号。 使用这两个控制信号，当晶体管（54）截止并且晶体管（56）导通时，两个晶体管（54,56）以互补和升压输出接通和断开，晶体管（57）从接通切换 并且晶体管（59）从接通切换到断开。 从而获得四倍的电压。

公开(公告)号：US5208517A

公开(公告)日：1993-05-04

申请号：US829328

申请日：1992-02-03

申请人： Takemi Beppu

发明人： Takemi Beppu

IPC分类号： H04N3/18 ,  H04N5/12 ,  H04N5/63

CPC分类号： H04N5/63

摘要： A television synchronous deflection circuit is generally comprised of a first power supply for supplying a D.C. voltage to a horizontal AFC circuit in the horizontal deflector of a television receiver, a second power supply for smoothing the flyback pulse and for supplying a predetermined D.C. voltage to a synchronous separator, and a comparator for comparing the output voltages of the first and second power supply circuits with each other. According to a comparison signal outputted from the comparator, the operation of the horizontal AFC circuit is controlled. For example, when the output voltage of the second power supply is less than a predetermined value, operation of the horizontal AFC circuit is prohibited; and when it is larger than the predetermined value, such prohibition is released.