公开(公告)号：US08507377B2

公开(公告)日：2013-08-13

申请号：US12764210

申请日：2010-04-21

申请人： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

发明人： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

IPC分类号： H01L21/4763

CPC分类号： G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.

摘要翻译： 一种制造半导体器件的方法，包括形成有集成电路的集成电路部分和包括围绕所述集成电路部分的金属膜的主壁部分的步骤包括以下步骤：在集成电路部分之间选择性地形成包括金属膜的副壁部分 电路部分和主壁部分，并联形成集成电路部分和主壁部分。 在主壁部的每个角部和所得到的半导体器件的集成电路部分之间设置有“L”形的副壁部。

公开(公告)号：US07755169B2

公开(公告)日：2010-07-13

申请号：US12357919

申请日：2009-01-22

申请人： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

发明人： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

IPC分类号： H01L23/544

CPC分类号： G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

摘要： A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

摘要翻译： 主壁部设置为围绕集成电路部。 在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。 因此，即使由于热处理等引起的应力集中，与常规的相比也不容易发生应力分散到主壁部和副壁部，因此层之间的剥离和裂纹不可能发生 艺术。 此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。 因此，可以确保极高的耐湿性。

公开(公告)号：US07587301B2

公开(公告)日：2009-09-08

申请号：US09781253

申请日：2001-02-13

申请人： Takumi Hasegawa

发明人： Takumi Hasegawa

IPC分类号： G06F17/50

CPC分类号： G06Q10/107 ,  G06F17/50 ,  G06F2217/04 ,  G06Q30/0203 ,  G06Q30/0621

摘要： A design data publicizing processing unit publicizes public design data and an editing program file to users through a network connected and based on personal information recited in an electronic mail received through the network, a received mail processing unit classifies user correction data attached to the received mail and registers the data in a user correction data DB, and user correction data stored in the user correction data DB is referred to or used as design data in product designing.

摘要翻译： 设计数据宣传处理单元通过连接的网络和基于通过网络接收的电子邮件中记载的个人信息向用户公布公共设计数据和编辑程序文件，接收的邮件处理单元对附接到接收到的邮件的用户校正数据进行分类 并将数据登记在用户校正数据DB中，并且存储在用户校正数据DB中的用户校正数据被引用或用作产品设计中的设计数据。

公开(公告)号：US07498659B2

公开(公告)日：2009-03-03

申请号：US11352273

申请日：2006-02-13

申请人： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

发明人： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada

IPC分类号： H01L23/544

CPC分类号： G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

摘要： A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

摘要翻译： 主壁部设置为围绕集成电路部。 在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。 因此，即使由于热处理等引起的应力集中，与常规的相比也不容易发生应力分散到主壁部和副壁部，因此层之间的剥离和裂纹不可能发生 艺术。 此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。 因此，可以确保极高的耐湿性。

公开(公告)号：US06371582B1

公开(公告)日：2002-04-16

申请号：US09320645

申请日：1999-05-27

申请人： Takumi Hasegawa

发明人： Takumi Hasegawa

IPC分类号： A47B9700

CPC分类号： A47B21/00 ,  A47B2097/006

摘要： A device for preventing a thin apparatus from overturning by fixing it with a fixing portion of a desk. The device prevents overturn of the thin apparatus, which is a tower type computer, or the like, as the apparatus is fixed to an overhanging part of the desk using a fixture which is a combination of a hook and a U-shaped bracket, when the thin apparatus is disposed in dead space at the back of, the side of, or under the desk.

摘要翻译： 一种用于通过用桌子的固定部分固定来防止薄装置翻倒的装置。 该设备防止翻转作为塔式计算机的薄设备等，因为该装置使用作为钩和U形支架的组合的固定装置固定到桌子的伸出部分上 该薄装置设置在桌面的背面，侧面或桌子下方的死空间中。

公开(公告)号：US20100240211A1

公开(公告)日：2010-09-23

申请号：US12764210

申请日：2010-04-21

申请人： Kenichi WATANABE ,  Michiari KAWANO ,  Hiroshi NAMBA ,  Kazuo SUKEGAWA ,  Takumi HASEGAWA ,  Toyoji SAWADA

发明人： Kenichi WATANABE ,  Michiari KAWANO ,  Hiroshi NAMBA ,  Kazuo SUKEGAWA ,  Takumi HASEGAWA ,  Toyoji SAWADA

IPC分类号： H01L21/768

CPC分类号： G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.

摘要翻译： 一种制造半导体器件的方法，包括形成有集成电路的集成电路部分和包括围绕所述集成电路部分的金属膜的主壁部分的步骤包括以下步骤：在集成电路部分之间选择性地形成包括金属膜的副壁部分 电路部分和主壁部分，并联形成集成电路部分和主壁部分。 在主壁部的每个角部和所得到的半导体器件的集成电路部分之间设置有“L”形的副壁部。

公开(公告)号：US20090172488A1

公开(公告)日：2009-07-02

申请号：US12340549

申请日：2008-12-19

申请人： Takumi Hasegawa ,  Motoyuki Sato ,  Tomoji Nakamura ,  Nobuo Konami ,  Jun Matsushima

发明人： Takumi Hasegawa ,  Motoyuki Sato ,  Tomoji Nakamura ,  Nobuo Konami ,  Jun Matsushima

IPC分类号： G01R31/3187

CPC分类号： G01R31/318533

摘要： A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.

摘要翻译： 半导体器件包括测试目标电路; 可扫描测试目标电路的扫描链; 形成提供给扫描链的测试图案的第一随机数生成电路; 与第一随机数生成电路分开设置的第二随机数生成电路; 以及使用由第二随机数生成电路产生的随机数来改变由第一随机数生成电路产生的随机数的随机数控制电路。 在半导体器件的测试中，由于扫描链的时钟周期不需要长于模式发生器的时钟周期，因此可以防止测试所需的模式发生器的时钟数 增加。 因此，可以防止测试时间增加。

公开(公告)号：US06889102B2

公开(公告)日：2005-05-03

申请号：US09808131

申请日：2001-03-15

申请人： Takumi Hasegawa

发明人： Takumi Hasegawa

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/50

摘要： A bug collection apparatus for use when a design modification is made to a bug in a drawing designed by using a computer aided design system, the apparatus formed by a first means for detecting whether the modification to the bug exceeds a pre-established criterion, and a second means for collecting and recording a bug information corresponding to the modification when the first means detecting that the modification exceeds the pre-established criterion.

摘要翻译： 一种用于当通过使用计算机辅助设计系统设计的图形中的错误进行设计修改时使用的错误收集装置，所述装置由用于检测对所述错误的修改是否超过预先建立的标准的第一装置形成;以及 第二装置，用于当第一装置检测出修改超过预先建立的标准时收集和记录与修改对应的错误信息。

公开(公告)号：US06515886B2

公开(公告)日：2003-02-04

申请号：US09820343

申请日：2001-03-29

申请人： Takumi Hasegawa

发明人： Takumi Hasegawa

IPC分类号： G11C506

CPC分类号： G11C5/06 ,  G11C5/14 ,  H01R12/7094 ,  Y10T307/766

摘要： In an electronic apparatus including an electronic circuit device, a board and a control circuit device for controlling the electronic circuit device, a socket for mounting the electronic circuit device is mounted on the board. The socket incorporates a switch for electrically connecting the control circuit device to a reference voltage line when the electronic circuit device is not mounted in the socket and electrically connecting the control circuit device to the electronic circuit device when the electronic circuit device is mounted in the socket.

摘要翻译： 在包括用于控制电子电路装置的电子电路装置，电路板和控制电路装置的电子装置中，安装电子电路装置的插座安装在电路板上。 当电子电路装置未安装在插座中时，插座包括用于将控制电路装置电连接到参考电压线的开关，并且当电子电路装置安装在插座中时，将控制电路装置电连接到电子电路装置 。

公开(公告)号：US5528511A

公开(公告)日：1996-06-18

申请号：US223722

申请日：1994-04-06

申请人： Takumi Hasegawa

发明人： Takumi Hasegawa

IPC分类号： G06F11/25 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： A delay time verifier to verify the delay time for a logic circuit using a time verification model prepared according to the graph theory. It comprises a verified model information file to store in advance the delay time verification information for each of the arcs in the time verification model including delay time for each rise/fall type of the signal at the start point node and the end point node of the arc, an invalidness specifier to specify an arc with invalid data and rise or fall of the signal to be invalidated for the arcs where only one of rise and fall signals is allowed to be valid, a modifier to modify the delay time verification information stored in the file so that the information for the arcs whose rise or fall signal specified by the invalidness specifier becomes invalid is modified, and a delay time verifier to verify the delay time of the logic circuit based on the delay time verification information after modification by the modifier.

摘要翻译： 延迟时间验证器，使用根据图论准备的时间验证模型来验证逻辑电路的延迟时间。 它包括一个经验证的模型信息文件，提前存储时间验证模型中每个弧的延迟时间验证信息，包括在起始点节点和终点节点处的信号的每个上升/下降类型的延迟时间 弧，无效指定符，用于指定具有无效数据的电弧以及允许上升和下降信号中的一个被允许有效的电弧的无效信号的上升或下降;修改器，用于修改存储在上升和下降信号中的延迟时间验证信息 该文件使得由无效指示符指定的上升或下降信号变为无效的弧的信息被修改，并且延迟时间验证器基于修改器修改后的延迟时间验证信息来验证逻辑电路的延迟时间 。