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    Semiconductor device with fuses
    7.
    发明授权
    Semiconductor device with fuses 有权
    带保险丝的半导体器件

    公开(公告)号：US06858914B2

    公开(公告)日：2005-02-22

    申请号：US10695876

    申请日：2003-10-30

    申请人： Ryota Nanjo ,  Satoshi Otsuka ,  Toyoji Sawada ,  Kazuo Sukegawa

    发明人： Ryota Nanjo ,  Satoshi Otsuka ,  Toyoji Sawada ,  Kazuo Sukegawa

    IPC分类号： H01L21/3205 ,  H01L21/762 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L23/525 ,  H01L23/58 ,  H01L27/04 ,  H01L29/00 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L21/76224 ,  H01L23/5258 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device has: a semiconductor substrate having a principal surface; a fuse circuit formed above the principal surface, the fuse circuit having fuse elements each having a predetermined breaking point; a first trench isolation region formed in a surface layer of the semiconductor substrate under the fuse circuit; and a plurality of active region dummies formed through the first trench isolation region in an area excepting a predetermined area around the predetermined breaking point. Although a dummy structure is formed also in a fuse circuit, a breaking margin is prevented from being lowered and a substrate damage is avoided, while surface flatness and line width controllability are ensured.

    摘要翻译： 半导体器件具有：具有主表面的半导体衬底; 熔丝电路，其形成在所述主表面上方，所述熔丝电路具有各自具有预定断裂点的熔丝元件; 形成在熔丝电路下的半导体衬底的表面层中的第一沟槽隔离区; 以及在除了预定断裂点周围的预定区域之外的区域中通过第一沟槽隔离区域形成的多个有源区域虚拟物。 虽然在熔丝电路中也形成虚拟结构，但是防止了断裂边缘的降低，并且避免了基板损伤，同时确保了表面平坦度和线宽度可控性。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP 审中-公开
    半导体器件及制造半导体集成电路芯片的方法

    公开(公告)号：US20100133659A1

    公开(公告)日：2010-06-03

    申请号：US12578901

    申请日：2009-10-14

    申请人： Akio Hara ,  Toyoji Sawada ,  Tsuyoshi Koyashiki ,  Hironori Fukaya

    发明人： Akio Hara ,  Toyoji Sawada ,  Tsuyoshi Koyashiki ,  Hironori Fukaya

    IPC分类号： H01L23/544 ,  H01L21/78

    CPC分类号： H01L21/78 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/172 ,  B28D5/0005 ,  B28D5/022 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film formed between and on the plurality of metal films, wherein a first metal film included in a first upper interlayer film of the plurality of interlayer films is positionally offset in a vertical direction to a second metal film included in a second lower interlayer film under the first interlayer film.

    摘要翻译： 一种半导体器件，包括形成在半导体衬底中的多个电路区域和形成在用于分离各个电路区域的电路区域周围的划线区域，划线区域具有多个层叠的夹层膜，其包括多个金属膜和光学 - 在多个金属膜之间形成透明绝缘膜，其中包括在所述多个中间膜中的第一上层间膜中的第一金属膜在与第二下层间膜中包括的第二金属膜垂直方向上位置偏移 在第一层间膜下。

    Self-testing circuit in semiconductor memory device
    9.
    发明授权
    Self-testing circuit in semiconductor memory device 有权
    半导体存储器件中的自检电路

    公开(公告)号：US07171592B2

    公开(公告)日：2007-01-30

    申请号：US10360862

    申请日：2003-02-10

    申请人： Kenji Togashi ,  Morihiko Hamada ,  Shigekazu Aoki ,  Katsumi Shigenobu ,  Yukio Saka ,  Yoshikazu Arisaka ,  Toyoji Sawada ,  Tadashi Asai

    发明人： Kenji Togashi ,  Morihiko Hamada ,  Shigekazu Aoki ,  Katsumi Shigenobu ,  Yukio Saka ,  Yoshikazu Arisaka ,  Toyoji Sawada ,  Tadashi Asai

    IPC分类号： G06F11/00

    CPC分类号： G11C29/4401 ,  G11C29/789 ,  G11C29/848

    摘要： A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.

    摘要翻译： 半导体存储器件包括具有简单结构的自检电路和自冗余电路。 自检电路包括比较电路，其将写入数据与读取数据相对于正常存储器块和冗余存储器块进行比较，以及判定电路，其基于多个比较结果信号来判定半导体存储器件是否良好或有缺陷 。 信号传送和保持电路连接在比较电路和判定电路之间，以将多个比较结果信号传送到判定电路，并将多个比较结果信号提供给自冗余电路作为测试结果。