公开(公告)号：US07072224B2

公开(公告)日：2006-07-04

申请号：US11284949

申请日：2005-11-23

申请人： Yoshinori Sakamoto ,  Tatsuya Bando

发明人： Yoshinori Sakamoto ,  Tatsuya Bando

IPC分类号： G11C11/34

CPC分类号： G11C16/3477 ,  G11C16/16

摘要： The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased. Upon completion of erasing data in the memory cell, erase verification is carried out.

摘要翻译： 要增加存储器单元的重写次数，并且显着提高数据读取的可靠性。 在要擦除存储器单元中的数据的情况下，切换要施加到每个存储单元的控制栅极的擦除电压，同时切换到任意不同电平的电压，作为控制栅极电压（=软擦除 电压）根据在每个存储单元的浮置栅极处累积的电荷量来实现，以便保持施加到存储单元的隧道膜的电压基本上恒定。 在接受擦除命令时，CPU向解码器提供控制信号，并且基于所得到的解码信号，擦除电压切换电路产生一定电平的软擦除电压。 之后，当从一个切换到另一个不同电平的软擦除电压时，存储单元中的数据被擦除。 在完成擦除存储器单元中的数据时，执行擦除验证。

公开(公告)号：US07068541B2

公开(公告)日：2006-06-27

申请号：US10700592

申请日：2003-11-05

申请人： Yoshinori Sakamoto ,  Tatsuya Bando

发明人： Yoshinori Sakamoto ,  Tatsuya Bando

IPC分类号： G11C11/34

CPC分类号： G11C16/3477 ,  G11C16/16

摘要： The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased. Upon completion of erasing data in the memory cell, erase verification is carried out.

公开(公告)号：US20060077718A1

公开(公告)日：2006-04-13

申请号：US11284949

申请日：2005-11-23

申请人： Yoshinori Sakamoto ,  Tatsuya Bando

发明人： Yoshinori Sakamoto ,  Tatsuya Bando

IPC分类号： G11C16/04

CPC分类号： G11C16/3477 ,  G11C16/16

摘要： The number of rewrites for memory cells is to be increased, and the reliability of data reading to be substantially improved. Where data in memory cells are to be erased, the switching of an erase voltage to be applied to the control gate of each memory cell, while switching from one to another of voltages of any different levels, as the control gate voltage (=soft erase voltage) is accomplished according to the quantity of electric charges accumulated at the floating gate of each memory cell so as to keep substantially constant the voltage applied to the tunnel film of the memory cell. Upon acceptance of an erase command, a CPU supplies a control signal to a decoder, and on the basis of the resultant decode signal an erase voltage switching circuit generates a soft erase voltage of a certain level. After that, while switching from one to another of soft erase voltages differing in level, data in the memory cell are erased. Upon completion of erasing data in the memory cell, erase verification is carried out.